fadder4.vhd

VHDL实现四位全加器

library ieee;
use ieee.std_logic_1164.all;
entity fadder4 is
port(a,b:in std_logic_vector(0 to 3);
     cin:in std_logic;
     so:out std_logic_vector(0 to 3);
     cout:out std_logic);
end entity fadder4;
architecture behave of fadder4 is
component fadder1
port(a,b,cin:in std_logic;
     co,so:out std_logic);
end component;
signal c:std_logic_vector(0 to 2);
begin
u1:fadder1 port map(a=>a(0),b=>b(0),cin=>cin,co=>c(0),so=>so(0));
u2:fadder1 port map(a=>a(1),b=>b(1),cin=>c(0),co=>c(1),so=>so(1));
u3:fadder1 port map(a=>a(2),b=>b(2),cin=>c(1),co=>c(2),so=>so(2));
u4:fadder1 port map(a=>a(3),b=>b(3),cin=>c(2),co=>cout,so=>so(3));
end behave;