vhdl1.vhd.bak

来自「VHDL实现四位全加器」· BAK 代码 · 共 12 行

library ieee;
use ieee.std_logic_1164.all;
entity f_adder is
port(a,b,ci:in std_logic;
co,so: out std_logic);
end entity f_adder;
architecture fd of f_adder is
begin 
 so<=a XOR b XOR ci;
 co<=(a AND b)OR(a XOR b)AND ci;
end architecture fd;