fifo.v

FIFO的源代码

module FIFO(Data_out,DIR,DOR,Clk,Data_in,Reset,Si,So);
output DIR;            //Full flag,0 valid
output DOR;            //Empty flag,0 valid
output[9:0] Data_out;
input Clk;
input Si; 
input So;
input Reset;           // FIFO reset;     
input[9:0] Data_in;

reg DIR;
reg DOR;
reg[9:0] Data_out;

reg[9:0] Ram_buf[15:0]; //buffer use in FIFO

reg[3:0] Wp;
reg[3:0] Rp;

integer i; 
 
always @ (negedge Clk)
  if(Reset)
    begin
      for(i=0;i<=15;i=i+1)
         Ram_buf[i] <= 0;
      DIR <= 1;
      DOR <= 0;
      Wp <= 0;
      Rp <= 15;
    end
  else
    begin
      if(Si)
         Write_FIFO;
      else if(So)
         Read_FIFO;
    end
    
task Write_FIFO;
  begin
    if(DIR)
      begin
        DOR <= 1;
        Ram_buf[Wp] <= Data_in;
        $display("Ram_buf[%h] = %h",Wp,Ram_buf[Wp]);
        if(Wp==15)
          Wp <= 0;
        else
          Wp <= Wp+1;
        if(Wp == Rp)  //Ram write full
           DIR <= 0;
        else
           DIR <= 1;         
        end
    else
      $display("FIFO has full!!!");
  end
endtask

task Read_FIFO;
  begin
   if(DOR)
    begin
      DIR <= 1;
      Data_out <= Ram_buf[Rp];
      if(Rp==15)
        Rp <= 0;
      else
        Rp <= Rp+1;
      if( ((Rp==15)&(Wp==1))||((Rp==14)&(Wp==0))||(Rp==Wp-2) )  //Ram read empty
        DOR <= 0;
      else    
        DOR <= 1;
    end
   else
     $display("FIFO has empty!!!");
  end
endtask
  


endmodule