counter24.hier_info

VHDL编写的万年历,已在实验箱上验证,目标芯片EP1C3T144C8

|counter24
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => count[5].CLK
reset => comb~0.IN0
reset => comb~1.IN0
reset => comb~2.IN0
reset => comb~3.IN0
reset => comb~4.IN0
reset => comb~5.IN0
reset => comb~6.IN0
reset => comb~7.IN0
reset => comb~8.IN0
reset => comb~9.IN0
reset => comb~10.IN0
reset => comb~11.IN0
din[0] => comb~4.IN1
din[0] => comb~11.IN1
din[1] => comb~3.IN1
din[1] => comb~10.IN1
din[2] => comb~2.IN1
din[2] => comb~9.IN1
din[3] => comb~1.IN1
din[3] => comb~8.IN1
din[4] => comb~0.IN1
din[4] => comb~7.IN1
din[5] => comb~5.IN1
din[5] => comb~6.IN1
dout[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= count[4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= count[5].DB_MAX_OUTPUT_PORT_TYPE