counter24.tan.qmsg

VHDL编写的万年历,已在实验箱上验证,目标芯片EP1C3T144C8

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[1\] register count\[2\] 394.17 MHz 2.537 ns Internal " "Info: Clock \"clk\" has Internal fmax of 394.17 MHz between source register \"count\[1\]\" and destination register \"count\[2\]\" (period= 2.537 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.335 ns + Longest register register " "Info: + Longest register to register delay is 2.335 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC_X16_Y1_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y1_N2; Fanout = 6; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "" { count[1] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.454 ns) 0.919 ns rtl~52 2 COMB LC_X16_Y1_N8 2 " "Info: 2: + IC(0.465 ns) + CELL(0.454 ns) = 0.919 ns; Loc. = LC_X16_Y1_N8; Fanout = 2; COMB Node = 'rtl~52'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "0.919 ns" { count[1] rtl~52 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.349 ns) + CELL(0.225 ns) 1.493 ns count\[0\]~215 3 COMB LC_X16_Y1_N0 3 " "Info: 3: + IC(0.349 ns) + CELL(0.225 ns) = 1.493 ns; Loc. = LC_X16_Y1_N0; Fanout = 3; COMB Node = 'count\[0\]~215'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "0.574 ns" { rtl~52 count[0]~215 } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.467 ns) 2.335 ns count\[2\] 4 REG LC_X16_Y1_N7 5 " "Info: 4: + IC(0.375 ns) + CELL(0.467 ns) = 2.335 ns; Loc. = LC_X16_Y1_N7; Fanout = 5; REG Node = 'count\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "0.842 ns" { count[0]~215 count[2] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.146 ns ( 49.08 % ) " "Info: Total cell delay = 1.146 ns ( 49.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.189 ns ( 50.92 % ) " "Info: Total interconnect delay = 1.189 ns ( 50.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "2.335 ns" { count[1] rtl~52 count[0]~215 count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.335 ns" { count[1] rtl~52 count[0]~215 count[2] } { 0.000ns 0.465ns 0.349ns 0.375ns } { 0.000ns 0.454ns 0.225ns 0.467ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.110 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "" { clk } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.547 ns) 2.110 ns count\[2\] 2 REG LC_X16_Y1_N7 5 " "Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X16_Y1_N7; Fanout = 5; REG Node = 'count\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "0.980 ns" { clk count[2] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.48 % ) " "Info: Total cell delay = 1.677 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.433 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.433 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "2.110 ns" { clk count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.110 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "" { clk } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.547 ns) 2.110 ns count\[1\] 2 REG LC_X16_Y1_N2 6 " "Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X16_Y1_N2; Fanout = 6; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "0.980 ns" { clk count[1] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.48 % ) " "Info: Total cell delay = 1.677 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.433 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.433 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "2.110 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "2.110 ns" { clk count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "2.110 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "2.335 ns" { count[1] rtl~52 count[0]~215 count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.335 ns" { count[1] rtl~52 count[0]~215 count[2] } { 0.000ns 0.465ns 0.349ns 0.375ns } { 0.000ns 0.454ns 0.225ns 0.467ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "2.110 ns" { clk count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "2.110 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[1\] count\[1\] 5.860 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[1\]\" through register \"count\[1\]\" is 5.860 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.110 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "" { clk } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.547 ns) 2.110 ns count\[1\] 2 REG LC_X16_Y1_N2 6 " "Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X16_Y1_N2; Fanout = 6; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "0.980 ns" { clk count[1] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.48 % ) " "Info: Total cell delay = 1.677 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.433 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.433 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "2.110 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.577 ns + Longest register pin " "Info: + Longest register to pin delay is 3.577 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC_X16_Y1_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y1_N2; Fanout = 6; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "" { count[1] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(1.634 ns) 3.577 ns dout\[1\] 2 PIN PIN_35 0 " "Info: 2: + IC(1.943 ns) + CELL(1.634 ns) = 3.577 ns; Loc. = PIN_35; Fanout = 0; PIN Node = 'dout\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "3.577 ns" { count[1] dout[1] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "G:/fpga/wogoproject/counter24/counter24.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns ( 45.68 % ) " "Info: Total cell delay = 1.634 ns ( 45.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.943 ns ( 54.32 % ) " "Info: Total interconnect delay = 1.943 ns ( 54.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "3.577 ns" { count[1] dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.577 ns" { count[1] dout[1] } { 0.000ns 1.943ns } { 0.000ns 1.634ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "2.110 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter24" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter24/db/counter24.quartus_db" { Floorplan "G:/fpga/wogoproject/counter24/" "" "3.577 ns" { count[1] dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.577 ns" { count[1] dout[1] } { 0.000ns 1.943ns } { 0.000ns 1.634ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 25 17:21:05 2008 " "Info: Processing ended: Fri Apr 25 17:21:05 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}