counter24.tan.rpt

VHDL编写的万年历,已在实验箱上验证,目标芯片EP1C3T144C8

; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[3] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 2.147 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 2.099 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 2.096 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 2.092 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 2.003 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 2.000 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 1.996 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[1] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 1.835 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[5] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 1.733 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[5] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 1.730 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[5] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 1.726 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[3] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 1.658 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[4] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 1.635 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[4] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 1.632 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[4] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 1.628 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 1.606 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 1.503 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[1] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 1.503 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[3] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 1.326 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 1.274 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 1.171 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[4] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 0.916 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[4] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 0.908 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 0.731 ns                ;
; N/A   ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[5] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 0.472 ns                ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+----------+---------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To      ; From Clock ;
+-------+--------------+------------+----------+---------+------------+
; N/A   ; None         ; 5.860 ns   ; count[1] ; dout[1] ; clk        ;
; N/A   ; None         ; 5.510 ns   ; count[4] ; dout[4] ; clk        ;
; N/A   ; None         ; 5.148 ns   ; count[0] ; dout[0] ; clk        ;
; N/A   ; None         ; 5.138 ns   ; count[2] ; dout[2] ; clk        ;
; N/A   ; None         ; 4.896 ns   ; count[5] ; dout[5] ; clk        ;
; N/A   ; None         ; 4.894 ns   ; count[3] ; dout[3] ; clk        ;
+-------+--------------+------------+----------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Fri Apr 25 17:21:04 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off counter24 -c counter24 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 394.17 MHz between source register "count[1]" and destination register "count[2]" (period= 2.537 ns)
    Info: + Longest register to register delay is 2.335 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y1_N2; Fanout = 6; REG Node = 'count[1]'
        Info: 2: + IC(0.465 ns) + CELL(0.454 ns) = 0.919 ns; Loc. = LC_X16_Y1_N8; Fanout = 2; COMB Node = 'rtl~52'
        Info: 3: + IC(0.349 ns) + CELL(0.225 ns) = 1.493 ns; Loc. = LC_X16_Y1_N0; Fanout = 3; COMB Node = 'count[0]~215'
        Info: 4: + IC(0.375 ns) + CELL(0.467 ns) = 2.335 ns; Loc. = LC_X16_Y1_N7; Fanout = 5; REG Node = 'count[2]'
        Info: Total cell delay = 1.146 ns ( 49.08 % )
        Info: Total interconnect delay = 1.189 ns ( 50.92 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.110 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X16_Y1_N7; Fanout = 5; REG Node = 'count[2]'
            Info: Total cell delay = 1.677 ns ( 79.48 % )
            Info: Total interconnect delay = 0.433 ns ( 20.52 % )
        Info: - Longest clock path from clock "clk" to source register is 2.110 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X16_Y1_N2; Fanout = 6; REG Node = 'count[1]'
            Info: Total cell delay = 1.677 ns ( 79.48 % )
            Info: Total interconnect delay = 0.433 ns ( 20.52 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock "clk" to destination pin "dout[1]" through register "count[1]" is 5.860 ns
    Info: + Longest clock path from clock "clk" to source register is 2.110 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X16_Y1_N2; Fanout = 6; REG Node = 'count[1]'
        Info: Total cell delay = 1.677 ns ( 79.48 % )
        Info: Total interconnect delay = 0.433 ns ( 20.52 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 3.577 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y1_N2; Fanout = 6; REG Node = 'count[1]'
        Info: 2: + IC(1.943 ns) + CELL(1.634 ns) = 3.577 ns; Loc. = PIN_35; Fanout = 0; PIN Node = 'dout[1]'
        Info: Total cell delay = 1.634 ns ( 45.68 % )
        Info: Total interconnect delay = 1.943 ns ( 54.32 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Apr 25 17:21:05 2008
    Info: Elapsed time: 00:00:02