📄 counter24.map.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--count[0] is count[0]
--operation mode is normal
count[0]_lut_out = !count[0];
count[0] = DFFEAS(count[0]_lut_out, clk, VCC, , , din[0], !reset, , );
--count[1] is count[1]
--operation mode is normal
count[1]_lut_out = !A1L5 & (count[1] $ count[0]);
count[1] = DFFEAS(count[1]_lut_out, clk, VCC, , , din[1], !reset, , );
--count[2] is count[2]
--operation mode is normal
count[2]_lut_out = A1L13;
count[2] = DFFEAS(count[2]_lut_out, clk, VCC, , , din[2], !reset, , );
--count[3] is count[3]
--operation mode is normal
count[3]_lut_out = A1L11;
count[3] = DFFEAS(count[3]_lut_out, clk, VCC, , , din[3], !reset, , );
--count[4] is count[4]
--operation mode is normal
count[4]_lut_out = count[4] $ (A1L29);
count[4] = DFFEAS(count[4]_lut_out, clk, VCC, , , din[4], !reset, , );
--count[5] is count[5]
--operation mode is normal
count[5]_lut_out = A1L12;
count[5] = DFFEAS(count[5]_lut_out, clk, VCC, , , din[5], !reset, , );
--A1L29 is rtl~51
--operation mode is normal
A1L29 = count[0] & count[3] & !count[1] & !count[2];
--A1L30 is rtl~52
--operation mode is normal
A1L30 = count[0] & count[1] & !count[2] & !count[3];
--A1L5 is count[0]~215
--operation mode is normal
A1L5 = A1L29 $ (!count[4] & count[5] & A1L30);
--A1L1 is add~142
--operation mode is normal
A1L1 = count[0] & count[1];
--A1L11 is count~217
--operation mode is normal
A1L11 = !A1L5 & (count[3] $ (count[2] & A1L1));
--A1L12 is count~219
--operation mode is normal
A1L12 = count[4] & (count[5] $ A1L29) # !count[4] & !A1L30 & count[5];
--A1L13 is count~220
--operation mode is normal
A1L13 = !A1L5 & (count[2] $ (count[0] & count[1]));
--clk is clk
--operation mode is input
clk = INPUT();
--din[0] is din[0]
--operation mode is input
din[0] = INPUT();
--reset is reset
--operation mode is input
reset = INPUT();
--din[1] is din[1]
--operation mode is input
din[1] = INPUT();
--din[2] is din[2]
--operation mode is input
din[2] = INPUT();
--din[3] is din[3]
--operation mode is input
din[3] = INPUT();
--din[4] is din[4]
--operation mode is input
din[4] = INPUT();
--din[5] is din[5]
--operation mode is input
din[5] = INPUT();
--dout[0] is dout[0]
--operation mode is output
dout[0] = OUTPUT(count[0]);
--dout[1] is dout[1]
--operation mode is output
dout[1] = OUTPUT(count[1]);
--dout[2] is dout[2]
--operation mode is output
dout[2] = OUTPUT(count[2]);
--dout[3] is dout[3]
--operation mode is output
dout[3] = OUTPUT(count[3]);
--dout[4] is dout[4]
--operation mode is output
dout[4] = OUTPUT(count[4]);
--dout[5] is dout[5]
--operation mode is output
dout[5] = OUTPUT(count[5]);
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