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📄 counter10.fit.eqn

📁 VHDL编写的万年历,已在实验箱上验证,目标芯片EP1C3T144C8
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--count[0] is count[0] at LC_X9_Y13_N8
--operation mode is normal

count[0]_lut_out = !count[0];
count[0] = DFFEAS(count[0]_lut_out, GLOBAL(clk), VCC, , , din[0], !GLOBAL(reset), , );


--count[2] is count[2] at LC_X9_Y13_N2
--operation mode is normal

count[2]_lut_out = count[2] $ (count[0] & (count[1]));
count[2] = DFFEAS(count[2]_lut_out, GLOBAL(clk), VCC, , , din[2], !GLOBAL(reset), , );


--A1L10Q is c~reg0 at LC_X9_Y13_N4
--operation mode is normal

A1L10Q_lut_out = !count[2] & count[3] & count[0] & !count[1];
A1L10Q = DFFEAS(A1L10Q_lut_out, GLOBAL(clk), GLOBAL(reset), , , , , , );


--count[1] is count[1] at LC_X9_Y13_N6
--operation mode is normal

count[1]_qfbk = count[1];
count[1]_lut_out = count[0] & !count[1]_qfbk & (count[2] # !count[3]) # !count[0] & (count[1]_qfbk);
count[1] = DFFEAS(count[1]_lut_out, GLOBAL(clk), VCC, , , din[1], !GLOBAL(reset), , );


--count[3] is count[3] at LC_X9_Y13_N5
--operation mode is normal

count[3]_qfbk = count[3];
count[3]_lut_out = count[2] & (count[3]_qfbk $ (count[0] & count[1])) # !count[2] & count[3]_qfbk & (count[1] # !count[0]);
count[3] = DFFEAS(count[3]_lut_out, GLOBAL(clk), VCC, , , din[3], !GLOBAL(reset), , );


--clk is clk at PIN_17
--operation mode is input

clk = INPUT();


--din[0] is din[0] at PIN_134
--operation mode is input

din[0] = INPUT();


--reset is reset at PIN_16
--operation mode is input

reset = INPUT();


--din[1] is din[1] at PIN_130
--operation mode is input

din[1] = INPUT();


--din[2] is din[2] at PIN_127
--operation mode is input

din[2] = INPUT();


--din[3] is din[3] at PIN_133
--operation mode is input

din[3] = INPUT();


--dout[0] is dout[0] at PIN_132
--operation mode is output

dout[0] = OUTPUT(count[0]);


--dout[1] is dout[1] at PIN_53
--operation mode is output

dout[1] = OUTPUT(count[1]);


--dout[2] is dout[2] at PIN_107
--operation mode is output

dout[2] = OUTPUT(count[2]);


--dout[3] is dout[3] at PIN_131
--operation mode is output

dout[3] = OUTPUT(count[3]);


--c is c at PIN_2
--operation mode is output

c = OUTPUT(A1L10Q);




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