counter10.tan.qmsg

VHDL编写的万年历,已在实验箱上验证,目标芯片EP1C3T144C8

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register count\[2\] count\[3\] 405.19 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 405.19 MHz between source register \"count\[2\]\" and destination register \"count\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.234 ns 1.234 ns 2.468 ns " "Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.002 ns + Longest register register " "Info: + Longest register to register delay is 1.002 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[2\] 1 REG LC_X9_Y13_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y13_N2; Fanout = 5; REG Node = 'count\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "" { count[2] } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.568 ns) 1.002 ns count\[3\] 2 REG LC_X9_Y13_N5 4 " "Info: 2: + IC(0.434 ns) + CELL(0.568 ns) = 1.002 ns; Loc. = LC_X9_Y13_N5; Fanout = 4; REG Node = 'count\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "1.002 ns" { count[2] count[3] } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.568 ns ( 56.69 % ) " "Info: Total cell delay = 0.568 ns ( 56.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.434 ns ( 43.31 % ) " "Info: Total interconnect delay = 0.434 ns ( 43.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "1.002 ns" { count[2] count[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.002 ns" { count[2] count[3] } { 0.000ns 0.434ns } { 0.000ns 0.568ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.128 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "" { clk } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns count\[3\] 2 REG LC_X9_Y13_N5 4 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X9_Y13_N5; Fanout = 4; REG Node = 'count\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "0.998 ns" { clk count[3] } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.81 % ) " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns ( 21.19 % ) " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "2.128 ns" { clk count[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 count[3] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.128 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "" { clk } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns count\[2\] 2 REG LC_X9_Y13_N2 5 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X9_Y13_N2; Fanout = 5; REG Node = 'count\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "0.998 ns" { clk count[2] } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.81 % ) " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns ( 21.19 % ) " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "2.128 ns" { clk count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "2.128 ns" { clk count[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 count[3] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "2.128 ns" { clk count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "1.002 ns" { count[2] count[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.002 ns" { count[2] count[3] } { 0.000ns 0.434ns } { 0.000ns 0.568ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "2.128 ns" { clk count[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 count[3] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "2.128 ns" { clk count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "" { count[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { count[3] } {  } {  } } } { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 21 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[1\] count\[1\] 6.275 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[1\]\" through register \"count\[1\]\" is 6.275 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.128 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "" { clk } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns count\[1\] 2 REG LC_X9_Y13_N6 5 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X9_Y13_N6; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "0.998 ns" { clk count[1] } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.81 % ) " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns ( 21.19 % ) " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "2.128 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.974 ns + Longest register pin " "Info: + Longest register to pin delay is 3.974 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC_X9_Y13_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y13_N6; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "" { count[1] } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.352 ns) + CELL(1.622 ns) 3.974 ns dout\[1\] 2 PIN PIN_53 0 " "Info: 2: + IC(2.352 ns) + CELL(1.622 ns) = 3.974 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'dout\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "3.974 ns" { count[1] dout[1] } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "G:/fpga/wogoproject/counter10/counter10.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns ( 40.82 % ) " "Info: Total cell delay = 1.622 ns ( 40.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.352 ns ( 59.18 % ) " "Info: Total interconnect delay = 2.352 ns ( 59.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "3.974 ns" { count[1] dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.974 ns" { count[1] dout[1] } { 0.000ns 2.352ns } { 0.000ns 1.622ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "2.128 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "counter10" "UNKNOWN" "V1" "G:/fpga/wogoproject/counter10/db/counter10.quartus_db" { Floorplan "G:/fpga/wogoproject/counter10/" "" "3.974 ns" { count[1] dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.974 ns" { count[1] dout[1] } { 0.000ns 2.352ns } { 0.000ns 1.622ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 25 16:24:54 2008 " "Info: Processing ended: Fri Apr 25 16:24:54 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}