counter10.vhd

来自「VHDL编写的万年历,已在实验箱上验证,目标芯片EP1C3T144C8」· VHDL 代码 · 共 36 行

--文件名：counter10.vhd。
--功能：10进制计数器，有进位C
--最后修改日期：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10 is
    Port ( clk : in std_logic;
           reset : in std_logic;
           din : in std_logic_vector(3 downto 0);
           dout : out std_logic_vector(3 downto 0);
		   c:out std_logic);
end counter10;
architecture Behavioral of counter10 is
   signal count : std_logic_vector(3 downto 0);
begin
    dout <= count;
	process(clk,reset,din)
	--这里的IF语句也和我先前的分频器差不多，但是编译没有出现分频器的错误Why
	begin
	   if reset='0'then
		 count <= din ;
		 c<='0';
       elsif rising_edge(clk) then
		   if  count = "1001" then
			   count <= "0000";
			   c<='1';
           else 
			   count <= count+1;
			   c<='0';
           end if;
      end if;
    end process;
end Behavioral;