wogodiv.vhd

来自「VHDL编写的万年历,已在实验箱上验证,目标芯片EP1C3T144C8」· VHDL 代码 · 共 28 行

--成功作品；以后总结
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY wogodiv IS
      PORT(
           CLK:IN STD_LOGIC;
           outclk:out std_logic);
end wogodiv;

ARCHITECTURE meter OF wogodiv IS
--晶振为20M ，那么Q最大必须有如下限定；下载到试验箱以后，相当准确
    SIGNAL q:integer range 0 to 19999999;
    signal a:std_logic;
BEGIN 
    
  PROCESS(CLK)
  BEGIN
       IF clk'event and clk='1' THEN
           q<=q+1;
           if q=19999999 then 
              q<=0;
              a<=not a;
           end if;
       end if;
  end process;
  outclk<=a;
end meter;