📄 wogodiv.fit.rpt
字号:
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 6 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
+---------------------------------------------+------------------------------+
+----------------------------+
; Advanced Data - General ;
+--------------------+-------+
; Name ; Value ;
+--------------------+-------+
; Status Code ; 0 ;
; Desired User Slack ; 0 ;
; Fit Attempts ; 1 ;
+--------------------+-------+
+----------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation ;
+-----------------------------------------------------------------------------+----------+
; Name ; Value ;
+-----------------------------------------------------------------------------+----------+
; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; 996945 ;
; Internal Atom Count - Fit Attempt 1 ; 53 ;
; LE/ALM Count - Fit Attempt 1 ; 53 ;
; LAB Count - Fit Attempt 1 ; 12 ;
; Outputs per Lab - Fit Attempt 1 ; 3.833 ;
; Inputs per LAB - Fit Attempt 1 ; 4.167 ;
; Global Inputs per LAB - Fit Attempt 1 ; 0.833 ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'global control signals' - Fit Attempt 1 ; 0:2;1:10 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2;1:10 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1 ; 0:2;1:10 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1 ; 0:8;1:4 ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1 ; 0:7;1:5 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:9;1:3 ;
; LEs in Chains - Fit Attempt 1 ; 25 ;
; LEs in Long Chains - Fit Attempt 1 ; 25 ;
; LABs with Chains - Fit Attempt 1 ; 3 ;
; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.010 ;
+-----------------------------------------------------------------------------+----------+
+----------------------------------------------+
; Advanced Data - Placement ;
+-------------------------------------+--------+
; Name ; Value ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Early Slack - Fit Attempt 1 ; 986357 ;
; Auto Fit Point 3 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; 995258 ;
; Auto Fit Point 4 - Fit Attempt 1 ; ff ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Late Slack - Fit Attempt 1 ; 995258 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_dat.dll - Fit Attempt 1 ; 0.070 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.020 ;
+-------------------------------------+--------+
+----------------------------------------------+
; Advanced Data - Routing ;
+-------------------------------------+--------+
; Name ; Value ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1 ; 994862 ;
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Peak Regional Wire - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; 993926 ;
; Late Slack - Fit Attempt 1 ; 993926 ;
; Late Slack - Fit Attempt 1 ; 993926 ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.090 ;
+-------------------------------------+--------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
Info: Processing started: Fri Apr 25 16:06:32 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off wogodiv -c wogodiv
Info: Selected device EP1C3T144C6 for design "wogodiv"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EP1C6T144C6 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "CLK" to use Global clock in PIN 16
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 4.540 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X23_Y7; Fanout = 3; REG Node = 'q[21]'
Info: 2: + IC(0.829 ns) + CELL(0.340 ns) = 1.169 ns⌨️ 快捷键说明
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