wogodiv.tan.rpt

VHDL编写的万年历,已在实验箱上验证,目标芯片EP1C3T144C8

; N/A                                     ; 288.27 MHz ( period = 3.469 ns )                    ; q[3]  ; q[14] ; CLK        ; CLK      ; None                        ; None                      ; 3.267 ns                ;
; N/A                                     ; 288.43 MHz ( period = 3.467 ns )                    ; q[7]  ; q[9]  ; CLK        ; CLK      ; None                        ; None                      ; 3.265 ns                ;
; N/A                                     ; 289.27 MHz ( period = 3.457 ns )                    ; q[19] ; q[21] ; CLK        ; CLK      ; None                        ; None                      ; 3.255 ns                ;
; N/A                                     ; 289.44 MHz ( period = 3.455 ns )                    ; q[6]  ; q[13] ; CLK        ; CLK      ; None                        ; None                      ; 3.253 ns                ;
; N/A                                     ; 289.52 MHz ( period = 3.454 ns )                    ; q[6]  ; q[10] ; CLK        ; CLK      ; None                        ; None                      ; 3.252 ns                ;
; N/A                                     ; 289.52 MHz ( period = 3.454 ns )                    ; q[6]  ; q[11] ; CLK        ; CLK      ; None                        ; None                      ; 3.252 ns                ;
; N/A                                     ; 289.52 MHz ( period = 3.454 ns )                    ; q[3]  ; q[22] ; CLK        ; CLK      ; None                        ; None                      ; 3.224 ns                ;
; N/A                                     ; 289.86 MHz ( period = 3.450 ns )                    ; q[3]  ; q[23] ; CLK        ; CLK      ; None                        ; None                      ; 3.220 ns                ;
; N/A                                     ; 289.94 MHz ( period = 3.449 ns )                    ; q[6]  ; q[16] ; CLK        ; CLK      ; None                        ; None                      ; 3.247 ns                ;
; N/A                                     ; 290.36 MHz ( period = 3.444 ns )                    ; q[7]  ; q[13] ; CLK        ; CLK      ; None                        ; None                      ; 3.242 ns                ;
; N/A                                     ; 290.70 MHz ( period = 3.440 ns )                    ; q[9]  ; q[18] ; CLK        ; CLK      ; None                        ; None                      ; 3.238 ns                ;
; N/A                                     ; 290.70 MHz ( period = 3.440 ns )                    ; q[0]  ; q[20] ; CLK        ; CLK      ; None                        ; None                      ; 3.238 ns                ;
; N/A                                     ; 291.04 MHz ( period = 3.436 ns )                    ; q[0]  ; q[21] ; CLK        ; CLK      ; None                        ; None                      ; 3.234 ns                ;
; N/A                                     ; 291.46 MHz ( period = 3.431 ns )                    ; q[12] ; a     ; CLK        ; CLK      ; None                        ; None                      ; 3.229 ns                ;
; N/A                                     ; 292.23 MHz ( period = 3.422 ns )                    ; q[2]  ; q[20] ; CLK        ; CLK      ; None                        ; None                      ; 3.220 ns                ;
; N/A                                     ; 292.40 MHz ( period = 3.420 ns )                    ; q[7]  ; q[16] ; CLK        ; CLK      ; None                        ; None                      ; 3.218 ns                ;
; N/A                                     ; 292.57 MHz ( period = 3.418 ns )                    ; q[2]  ; q[21] ; CLK        ; CLK      ; None                        ; None                      ; 3.216 ns                ;
; N/A                                     ; 293.17 MHz ( period = 3.411 ns )                    ; q[4]  ; q[20] ; CLK        ; CLK      ; None                        ; None                      ; 3.209 ns                ;
; N/A                                     ; 293.51 MHz ( period = 3.407 ns )                    ; q[4]  ; q[21] ; CLK        ; CLK      ; None                        ; None                      ; 3.205 ns                ;
; N/A                                     ; 294.46 MHz ( period = 3.396 ns )                    ; q[0]  ; q[19] ; CLK        ; CLK      ; None                        ; None                      ; 3.194 ns                ;
; N/A                                     ; 294.64 MHz ( period = 3.394 ns )                    ; q[6]  ; q[21] ; CLK        ; CLK      ; None                        ; None                      ; 3.192 ns                ;
; N/A                                     ; 294.64 MHz ( period = 3.394 ns )                    ; q[13] ; a     ; CLK        ; CLK      ; None                        ; None                      ; 3.192 ns                ;
; N/A                                     ; 294.72 MHz ( period = 3.393 ns )                    ; q[13] ; q[21] ; CLK        ; CLK      ; None                        ; None                      ; 3.191 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;       ;       ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------+
; tco                                                            ;
+-------+--------------+------------+------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To     ; From Clock ;
+-------+--------------+------------+------+--------+------------+
; N/A   ; None         ; 5.385 ns   ; a    ; outclk ; CLK        ;
+-------+--------------+------------+------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Fri Apr 25 16:06:53 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off wogodiv -c wogodiv --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 173.82 MHz between source register "q[21]" and destination register "q[20]" (period= 5.753 ns)
    Info: + Longest register to register delay is 5.551 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y7_N4; Fanout = 3; REG Node = 'q[21]'
        Info: 2: + IC(0.985 ns) + CELL(0.340 ns) = 1.325 ns; Loc. = LC_X22_Y5_N8; Fanout = 1; COMB Node = 'rtl~206'
        Info: 3: + IC(0.926 ns) + CELL(0.454 ns) = 2.705 ns; Loc. = LC_X21_Y6_N6; Fanout = 1; COMB Node = 'rtl~210'
        Info: 4: + IC(0.910 ns) + CELL(0.340 ns) = 3.955 ns; Loc. = LC_X22_Y7_N2; Fanout = 9; COMB Node = 'rtl~0'
        Info: 5: + IC(1.028 ns) + CELL(0.568 ns) = 5.551 ns; Loc. = LC_X21_Y6_N0; Fanout = 4; REG Node = 'q[20]'
        Info: Total cell delay = 1.702 ns ( 30.66 % )
        Info: Total interconnect delay = 3.849 ns ( 69.34 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.138 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'CLK'
            Info: 2: + IC(0.461 ns) + CELL(0.547 ns) = 2.138 ns; Loc. = LC_X21_Y6_N0; Fanout = 4; REG Node = 'q[20]'
            Info: Total cell delay = 1.677 ns ( 78.44 % )
            Info: Total interconnect delay = 0.461 ns ( 21.56 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.138 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'CLK'
            Info: 2: + IC(0.461 ns) + CELL(0.547 ns) = 2.138 ns; Loc. = LC_X23_Y7_N4; Fanout = 3; REG Node = 'q[21]'
            Info: Total cell delay = 1.677 ns ( 78.44 % )
            Info: Total interconnect delay = 0.461 ns ( 21.56 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock "CLK" to destination pin "outclk" through register "a" is 5.385 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.138 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'CLK'
        Info: 2: + IC(0.461 ns) + CELL(0.547 ns) = 2.138 ns; Loc. = LC_X23_Y7_N5; Fanout = 2; REG Node = 'a'
        Info: Total cell delay = 1.677 ns ( 78.44 % )
        Info: Total interconnect delay = 0.461 ns ( 21.56 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 3.074 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y7_N5; Fanout = 2; REG Node = 'a'
        Info: 2: + IC(1.452 ns) + CELL(1.622 ns) = 3.074 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'outclk'
        Info: Total cell delay = 1.622 ns ( 52.77 % )
        Info: Total interconnect delay = 1.452 ns ( 47.23 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Apr 25 16:06:53 2008
    Info: Elapsed time: 00:00:01