okclk.tan.rpt

VHDL编写的万年历,已在实验箱上验证,目标芯片EP1C3T144C8

; N/A   ; None         ; 27.287 ns  ; counter24:inst2|count[0]  ; H24Out[0] ; clk        ;
; N/A   ; None         ; 26.944 ns  ; counter24:inst2|count[4]  ; H24Out[4] ; clk        ;
; N/A   ; None         ; 21.390 ns  ; counter6:inst11|count[2]  ; M6OUT[2]  ; clk        ;
; N/A   ; None         ; 21.145 ns  ; counter6:inst11|count[1]  ; M6OUT[1]  ; clk        ;
; N/A   ; None         ; 21.143 ns  ; counter6:inst11|count[0]  ; M6OUT[0]  ; clk        ;
; N/A   ; None         ; 17.808 ns  ; counter10:inst10|count[2] ; M10OUT[2] ; clk        ;
; N/A   ; None         ; 17.725 ns  ; counter10:inst10|count[3] ; M10OUT[3] ; clk        ;
; N/A   ; None         ; 17.716 ns  ; counter10:inst10|count[1] ; M10OUT[1] ; clk        ;
; N/A   ; None         ; 17.473 ns  ; counter10:inst10|count[0] ; M10OUT[0] ; clk        ;
; N/A   ; None         ; 13.351 ns  ; counter6:inst|count[0]    ; S6Out[0]  ; clk        ;
; N/A   ; None         ; 13.350 ns  ; counter6:inst|count[1]    ; S6Out[1]  ; clk        ;
; N/A   ; None         ; 13.343 ns  ; counter6:inst|count[2]    ; S6Out[2]  ; clk        ;
; N/A   ; None         ; 10.933 ns  ; counter10:inst1|count[0]  ; S10Out[0] ; clk        ;
; N/A   ; None         ; 10.728 ns  ; counter10:inst1|count[3]  ; S10Out[3] ; clk        ;
; N/A   ; None         ; 10.717 ns  ; counter10:inst1|count[2]  ; S10Out[2] ; clk        ;
; N/A   ; None         ; 10.709 ns  ; counter10:inst1|count[1]  ; S10Out[1] ; clk        ;
+-------+--------------+------------+---------------------------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Sat Apr 26 10:47:26 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off OkClk -c OkClk --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "wogodiv:inst3|a" as buffer
    Info: Detected ripple clock "counter10:inst1|c" as buffer
    Info: Detected ripple clock "counter6:inst|c" as buffer
    Info: Detected ripple clock "counter10:inst10|c" as buffer
    Info: Detected ripple clock "counter6:inst11|c" as buffer
Info: Clock "clk" has Internal fmax of 179.89 MHz between source register "wogodiv:inst3|q[21]" and destination register "wogodiv:inst3|q[16]" (period= 5.559 ns)
    Info: + Longest register to register delay is 5.357 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y6_N1; Fanout = 3; REG Node = 'wogodiv:inst3|q[21]'
        Info: 2: + IC(0.983 ns) + CELL(0.340 ns) = 1.323 ns; Loc. = LC_X16_Y5_N8; Fanout = 1; COMB Node = 'rtl~370'
        Info: 3: + IC(0.948 ns) + CELL(0.225 ns) = 2.496 ns; Loc. = LC_X17_Y6_N3; Fanout = 1; COMB Node = 'rtl~374'
        Info: 4: + IC(0.905 ns) + CELL(0.340 ns) = 3.741 ns; Loc. = LC_X16_Y7_N1; Fanout = 9; COMB Node = 'rtl~6'
        Info: 5: + IC(1.048 ns) + CELL(0.568 ns) = 5.357 ns; Loc. = LC_X17_Y6_N9; Fanout = 3; REG Node = 'wogodiv:inst3|q[16]'
        Info: Total cell delay = 1.473 ns ( 27.50 % )
        Info: Total interconnect delay = 3.884 ns ( 72.50 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.138 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'clk'
            Info: 2: + IC(0.461 ns) + CELL(0.547 ns) = 2.138 ns; Loc. = LC_X17_Y6_N9; Fanout = 3; REG Node = 'wogodiv:inst3|q[16]'
            Info: Total cell delay = 1.677 ns ( 78.44 % )
            Info: Total interconnect delay = 0.461 ns ( 21.56 % )
        Info: - Longest clock path from clock "clk" to source register is 2.138 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'clk'
            Info: 2: + IC(0.461 ns) + CELL(0.547 ns) = 2.138 ns; Loc. = LC_X17_Y6_N1; Fanout = 3; REG Node = 'wogodiv:inst3|q[21]'
            Info: Total cell delay = 1.677 ns ( 78.44 % )
            Info: Total interconnect delay = 0.461 ns ( 21.56 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock "clk" to destination pin "H24Out[2]" through register "counter24:inst2|count[2]" is 27.505 ns
    Info: + Longest clock path from clock "clk" to source register is 22.712 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'clk'
        Info: 2: + IC(0.461 ns) + CELL(0.720 ns) = 2.311 ns; Loc. = LC_X17_Y6_N4; Fanout = 6; REG Node = 'wogodiv:inst3|a'
        Info: 3: + IC(3.535 ns) + CELL(0.720 ns) = 6.566 ns; Loc. = LC_X26_Y6_N6; Fanout = 4; REG Node = 'counter10:inst1|c'
        Info: 4: + IC(2.838 ns) + CELL(0.720 ns) = 10.124 ns; Loc. = LC_X12_Y13_N6; Fanout = 5; REG Node = 'counter6:inst|c'
        Info: 5: + IC(3.651 ns) + CELL(0.720 ns) = 14.495 ns; Loc. = LC_X10_Y8_N2; Fanout = 4; REG Node = 'counter10:inst10|c'
        Info: 6: + IC(3.314 ns) + CELL(0.720 ns) = 18.529 ns; Loc. = LC_X6_Y13_N4; Fanout = 6; REG Node = 'counter6:inst11|c'
        Info: 7: + IC(3.636 ns) + CELL(0.547 ns) = 22.712 ns; Loc. = LC_X17_Y4_N8; Fanout = 5; REG Node = 'counter24:inst2|count[2]'
        Info: Total cell delay = 5.277 ns ( 23.23 % )
        Info: Total interconnect delay = 17.435 ns ( 76.77 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 4.620 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y4_N8; Fanout = 5; REG Node = 'counter24:inst2|count[2]'
        Info: 2: + IC(2.986 ns) + CELL(1.634 ns) = 4.620 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'H24Out[2]'
        Info: Total cel