📄 counter6.tan.rpt
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Timing Analyzer report for counter6
Fri Apr 25 16:54:22 2008
Version 5.1 Build 176 10/26/2005 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+----------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+----------+----------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 5.680 ns ; count[1] ; dout[1] ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[1] ; count[2] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+----------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[1] ; count[2] ; clk ; clk ; None ; None ; 0.992 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[1] ; count[1] ; clk ; clk ; None ; None ; 0.987 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; count[1] ; clk ; clk ; None ; None ; 0.889 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; c~reg0 ; clk ; clk ; None ; None ; 0.884 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[2] ; count[2] ; clk ; clk ; None ; None ; 0.883 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[1] ; c~reg0 ; clk ; clk ; None ; None ; 0.802 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[2] ; clk ; clk ; None ; None ; 0.694 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; c~reg0 ; clk ; clk ; None ; None ; 0.693 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[1] ; clk ; clk ; None ; None ; 0.688 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count[0] ; count[0] ; clk ; clk ; None ; None ; 0.687 ns ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+----------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+----------+---------+------------+
; N/A ; None ; 5.680 ns ; count[1] ; dout[1] ; clk ;
; N/A ; None ; 5.052 ns ; count[2] ; dout[2] ; clk ;
; N/A ; None ; 4.934 ns ; count[0] ; dout[0] ; clk ;
; N/A ; None ; 4.793 ns ; c~reg0 ; c ; clk ;
+-------+--------------+------------+----------+---------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
Info: Processing started: Fri Apr 25 16:54:21 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off counter6 -c counter6 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 405.19 MHz between source register "count[1]" and destination register "count[2]"
Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.992 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y2_N2; Fanout = 4; REG Node = 'count[1]'
Info: 2: + IC(0.424 ns) + CELL(0.568 ns) = 0.992 ns; Loc. = LC_X26_Y2_N5; Fanout = 4; REG Node = 'count[2]'
Info: Total cell delay = 0.568 ns ( 57.26 % )
Info: Total interconnect delay = 0.424 ns ( 42.74 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.110 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X26_Y2_N5; Fanout = 4; REG Node = 'count[2]'
Info: Total cell delay = 1.677 ns ( 79.48 % )
Info: Total interconnect delay = 0.433 ns ( 20.52 % )
Info: - Longest clock path from clock "clk" to source register is 2.110 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X26_Y2_N2; Fanout = 4; REG Node = 'count[1]'
Info: Total cell delay = 1.677 ns ( 79.48 % )
Info: Total interconnect delay = 0.433 ns ( 20.52 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock "clk" to destination pin "dout[1]" through register "count[1]" is 5.680 ns
Info: + Longest clock path from clock "clk" to source register is 2.110 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X26_Y2_N2; Fanout = 4; REG Node = 'count[1]'
Info: Total cell delay = 1.677 ns ( 79.48 % )
Info: Total interconnect delay = 0.433 ns ( 20.52 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Longest register to pin delay is 3.397 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y2_N2; Fanout = 4; REG Node = 'count[1]'
Info: 2: + IC(1.775 ns) + CELL(1.622 ns) = 3.397 ns; Loc. = PIN_110; Fanout = 0; PIN Node = 'dout[1]'
Info: Total cell delay = 1.622 ns ( 47.75 % )
Info: Total interconnect delay = 1.775 ns ( 52.25 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Fri Apr 25 16:54:21 2008
Info: Elapsed time: 00:00:01
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