counter6.fit.rpt

VHDL编写的万年历,已在实验箱上验证,目标芯片EP1C3T144C8

; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+---------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                 ;
+-----------------------------------------------------------------------------+---------+
; Name                                                                        ; Value   ;
+-----------------------------------------------------------------------------+---------+
; Auto Fit Point 1 - Fit Attempt 1                                            ; ff      ;
; Mid Wire Use - Fit Attempt 1                                                ; 0       ;
; Mid Slack - Fit Attempt 1                                                   ; 998938  ;
; Internal Atom Count - Fit Attempt 1                                         ; 5       ;
; LE/ALM Count - Fit Attempt 1                                                ; 5       ;
; LAB Count - Fit Attempt 1                                                   ; 2       ;
; Outputs per Lab - Fit Attempt 1                                             ; 2.000   ;
; Inputs per LAB - Fit Attempt 1                                              ; 2.000   ;
; Global Inputs per LAB - Fit Attempt 1                                       ; 1.000   ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1    ; 0:1;1:1 ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                             ; 0:2     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                        ; 0:1;1:1 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                       ; 0:1;1:1 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                 ; 0:1;2:1 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                  ; 0:1;2:1 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1        ; 0:2     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1          ; 0:1;1:1 ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1 ; 0:1;1:1 ;
; LAB Constraint 'global control signals' - Fit Attempt 1                     ; 0:1;3:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                 ; 0:1;1:1 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1            ; 0:1;1:1 ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                            ; 0:1;2:1 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                          ; 0:2     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                        ; 0:1;1:1 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                   ; 0:2     ;
; LEs in Chains - Fit Attempt 1                                               ; 0       ;
; LEs in Long Chains - Fit Attempt 1                                          ; 0       ;
; LABs with Chains - Fit Attempt 1                                            ; 0       ;
; LABs with Multiple Chains - Fit Attempt 1                                   ; 0       ;
; Time - Fit Attempt 1                                                        ; 0       ;
; Time in tsm_tan.dll - Fit Attempt 1                                         ; 0.020   ;
+-----------------------------------------------------------------------------+---------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 0      ;
; Early Slack - Fit Attempt 1         ; 999037 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 0      ;
; Mid Slack - Fit Attempt 1           ; 999037 ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Late Wire Use - Fit Attempt 1       ; 0      ;
; Late Slack - Fit Attempt 1          ; 999037 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_dat.dll - Fit Attempt 1 ; 0.100  ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.010  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; 998674 ;
; Mid Slack - Fit Attempt 1           ; 998314 ;
; Late Slack - Fit Attempt 1          ; 998314 ;
; Late Slack - Fit Attempt 1          ; 998314 ;
; Late Wire Use - Fit Attempt 1       ; 0      ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.050  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Fri Apr 25 16:54:02 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off counter6 -c counter6
Info: Selected device EP1C3T144C6 for design "counter6"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C6T144C6 is compatible
Info: No exact pin location assignment(s) for 9 pins of 9 total pins
    Info: Pin dout[0] not assigned to an exact location on the device
    Info: Pin dout[1] not assigned to an exact location on the device
    Info: Pin dout[2] not assigned to an exact location on the device
    Info: Pin c not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin din[0] not assigned to an exact location on the device
    Info: Pin reset not assigned to an exact location on the device
    Info: Pin din[1] not assigned to an exact location on the device
    Info: Pin din[2] not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 17
Info: Automatically promoted signal "reset" to use Global clock in PIN 16
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 7 (unused VREF, 3.30 VCCIO, 3 input, 4 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics