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📄 okclk.fit.talkback.xml

📁 VHDL编写的万年历,已在实验箱上验证,目标芯片EP1C3T144C8
💻 XML
📖 第 1 页 / 共 4 页
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		<name>S6Out[2]</name>
		<pin__>122</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>18</x_coordinate>
		<y_coordinate>14</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
		<load>Unspecified</load>
	</row>
</output_pins>
<i_o_bank_usage>
	<row>
		<i_o_bank>1</i_o_bank>
		<usage>9 / 22 ( 41 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>2</i_o_bank>
		<usage>17 / 28 ( 61 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>3</i_o_bank>
		<usage>5 / 26 ( 19 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>4</i_o_bank>
		<usage>13 / 28 ( 46 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
</i_o_bank_usage>
<advanced_data___general>
	<row>
		<name>Status Code</name>
		<value>0</value>
	</row>
	<row>
		<name>Desired User Slack</name>
		<value>0</value>
	</row>
	<row>
		<name>Fit Attempts</name>
		<value>1</value>
	</row>
</advanced_data___general>
<advanced_data___placement_preparation>
	<row>
		<name>Auto Fit Point 1 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Mid Wire Use - Fit Attempt 1</name>
		<value>1</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>996945</value>
	</row>
	<row>
		<name>Internal Atom Count - Fit Attempt 1</name>
		<value>82</value>
	</row>
	<row>
		<name>LE/ALM Count - Fit Attempt 1</name>
		<value>82</value>
	</row>
	<row>
		<name>LAB Count - Fit Attempt 1</name>
		<value>19</value>
	</row>
	<row>
		<name>Outputs per Lab - Fit Attempt 1</name>
		<value>3.737</value>
	</row>
	<row>
		<name>Inputs per LAB - Fit Attempt 1</name>
		<value>4.211</value>
	</row>
	<row>
		<name>Global Inputs per LAB - Fit Attempt 1</name>
		<value>1.053</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global clock / CE pair + async load&apos; - Fit Attempt 1</name>
		<value>0:14;1:5</value>
	</row>
	<row>
		<name>LAB Constraint &apos;ce + sync load&apos; - Fit Attempt 1</name>
		<value>0:19</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global controls&apos; - Fit Attempt 1</name>
		<value>0:14;1:5</value>
	</row>
	<row>
		<name>LAB Constraint &apos;un-route combination&apos; - Fit Attempt 1</name>
		<value>0:14;1:5</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global with asyn_clear&apos; - Fit Attempt 1</name>
		<value>0:14;1:1;2:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;un-route with async_clear&apos; - Fit Attempt 1</name>
		<value>0:14;1:1;2:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global async clear + sync clear&apos; - Fit Attempt 1</name>
		<value>0:19</value>
	</row>
	<row>
		<name>LAB Constraint &apos;global non-clock/non-asynch_clear&apos; - Fit Attempt 1</name>
		<value>0:14;1:5</value>
	</row>
	<row>
		<name>LAB Constraint &apos;ygr_cl_ngclk_gclkce_sload_aload_constraint&apos; - Fit Attempt 1</name>
		<value>0:14;1:5</value>
	</row>
	<row>
		<name>LAB Constraint &apos;global control signals&apos; - Fit Attempt 1</name>
		<value>0:3;1:11;2:1;3:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;clock / ce pair constraint&apos; - Fit Attempt 1</name>
		<value>0:3;1:16</value>
	</row>
	<row>
		<name>LAB Constraint &apos;aload_aclr pair with aload used&apos; - Fit Attempt 1</name>
		<value>0:14;1:5</value>
	</row>
	<row>
		<name>LAB Constraint &apos;aload_aclr pair&apos; - Fit Attempt 1</name>
		<value>0:3;1:12;2:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;sload_sclear pair&apos; - Fit Attempt 1</name>
		<value>0:15;1:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;invert_a constraint&apos; - Fit Attempt 1</name>
		<value>0:9;1:10</value>
	</row>
	<row>
		<name>LAB Constraint &apos;has placement constraint&apos; - Fit Attempt 1</name>
		<value>0:16;1:3</value>
	</row>
	<row>
		<name>LEs in Chains - Fit Attempt 1</name>
		<value>25</value>
	</row>
	<row>
		<name>LEs in Long Chains - Fit Attempt 1</name>
		<value>25</value>
	</row>
	<row>
		<name>LABs with Chains - Fit Attempt 1</name>
		<value>3</value>
	</row>
	<row>
		<name>LABs with Multiple Chains - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>0</value>
	</row>
</advanced_data___placement_preparation>
<advanced_data___placement>
	<row>
		<name>Auto Fit Point 2 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Early Wire Use - Fit Attempt 1</name>
		<value>1</value>
	</row>
	<row>
		<name>Early Slack - Fit Attempt 1</name>
		<value>988073</value>
	</row>
	<row>
		<name>Auto Fit Point 3 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Mid Wire Use - Fit Attempt 1</name>
		<value>2</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>995273</value>
	</row>
	<row>
		<name>Auto Fit Point 4 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Late Wire Use - Fit Attempt 1</name>
		<value>2</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>995273</value>
	</row>
	<row>
		<name>Auto Fit Point 5 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time in tsm_dat.dll - Fit Attempt 1</name>
		<value>0.090</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.030</value>
	</row>
</advanced_data___placement>
<advanced_data___routing>
	<row>
		<name>Early Slack - Fit Attempt 1</name>
		<value>995014</value>
	</row>
	<row>
		<name>Early Wire Use - Fit Attempt 1</name>
		<value>2</value>
	</row>
	<row>
		<name>Peak Regional Wire - Fit Attempt 1</name>
		<value>1</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>994175</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>994175</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>994175</value>
	</row>
	<row>
		<name>Late Wire Use - Fit Attempt 1</name>
		<value>2</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>1</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.170</value>
	</row>
</advanced_data___routing>
<compilation_summary>
	<flow_status>Successful - Sat Apr 26 10:47:11 2008</flow_status>
	<quartus_ii_version>5.1 Build 176 10/26/2005 SJ Web Edition</quartus_ii_version>
	<revision_name>OkClk</revision_name>
	<top_level_entity_name>OkClk</top_level_entity_name>
	<family>Cyclone</family>
	<device>EP1C3T144C6</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>81 / 2,910 ( 3 % )</total_logic_elements>
	<total_pins>42 / 104 ( 40 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>0 / 59,904 ( 0 % )</total_memory_bits>
	<total_plls>0 / 1 ( 0 % )</total_plls>
</compilation_summary>
<compile_id>C5E6EBE2</compile_id>
<files>
	<top>G:/fpga/wogoproject/Backup/OkClk/wogodiv/OkClk.bdf</top>
	<extensions>
		<ext ext_name="bsf">4</ext>
		<ext ext_name="cdf">1</ext>
		<ext ext_name="qpf">4</ext>
		<ext ext_name="vhd">4</ext>
		<ext ext_name="rpt">20</ext>
		<ext ext_name="done">4</ext>
		<ext ext_name="eqn">8</ext>
		<ext ext_name="summary">12</ext>
		<ext ext_name="pin">4</ext>
		<ext ext_name="pof">4</ext>
		<ext ext_name="qsf">4</ext>
		<ext ext_name="qws">4</ext>
		<ext ext_name="sof">4</ext>
		<ext ext_name="bdf">1</ext>
	</extensions>
	<sub_files>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.bsf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.cdf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.qpf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.vhd</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.asm.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.done</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.fit.eqn</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.fit.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.fit.summary</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.flow.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.map.eqn</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.map.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.map.summary</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.pin</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.pof</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.qsf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.qws</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.sof</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.tan.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/wogodiv.tan.summary</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.bsf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.qpf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.vhd</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.asm.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.done</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.fit.eqn</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.fit.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.fit.summary</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.flow.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.map.eqn</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.map.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.map.summary</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.pin</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.pof</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.qsf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.qws</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.sof</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.tan.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter24/counter24.tan.summary</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.bsf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.qpf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.vhd</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.asm.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.done</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.fit.eqn</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.fit.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.fit.summary</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.flow.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.map.eqn</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.map.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.map.summary</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.pin</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.pof</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.qsf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.qws</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.sof</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.tan.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter10/counter10.tan.summary</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.bsf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.qpf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.vhd</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.asm.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.done</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.fit.eqn</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.fit.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.fit.summary</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.flow.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.map.eqn</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.map.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.map.summary</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.pin</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.pof</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.qsf</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.qws</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.sof</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.tan.rpt</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/counter6/counter6.tan.summary</sub_file>
		<sub_file>G:/fpga/wogoproject/Backup/OkClk/wogodiv/OkClk.bdf</sub_file>
	</sub_files>
</files>
<architecture>
	<family>Cyclone</family>
	<auto_device>OFF</auto_device>
	<device>EP1C3T144C6</device>
</architecture>
<pkg_io>
	<pin_std count="44">LVTTL</pin_std>
</pkg_io>
<research>
	<le_sclr>0</le_sclr>
	<le_aclr>50</le_aclr>
	<le_aload>20</le_aload>
	<le_sload>12</le_sload>
	<le_inverta>0</le_inverta>
	<le_carry_in>23</le_carry_in>
	<le_ce>0</le_ce>
	<le_clk>50</le_clk>
	<le_ce_sload>0</le_ce_sload>
	<pin_sclr>0</pin_sclr>
	<pin_aclr>0</pin_aclr>
	<pin_ce_in>0</pin_ce_in>
	<pin_ce_out>0</pin_ce_out>
</research>
</talkback>

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