okclk.tan.talkback.xml

VHDL编写的万年历,已在实验箱上验证,目标芯片EP1C3T144C8

<!--
This XML file (created on Sat Apr 26 10:47:27 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>00e04ce841ba</host_id>
	<nic_id>00e04ce841ba</nic_id>
	<cdrive_id>b87c0ca6</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Sat Apr 26 10:47:27 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1309</cpu_freq>
	</cpu>
	<ram units="MB">256</ram>
</machine>
<top_file>G:/fpga/wogoproject/Backup/OkClk/OkClk</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off OkClk -c OkClk --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings</info>
	<info>Info: Elapsed time: 00:00:02</info>
	<info>Info: Processing ended: Sat Apr 26 10:47:27 2008</info>
	<info>Info: tco from clock &quot;clk&quot; to destination pin &quot;H24Out[2]&quot; through register &quot;counter24:inst2|count[2]&quot; is 27.505 ns</info>
	<info>Info: + Longest register to pin delay is 4.620 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>27.505 ns</actual>
	</nonclk>
	<clk>
		<name>clk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>179.89 MHz ( period = 5.559 ns )</actual>
	</clk>
</performance>
<compile_id>7A2C5AC9</compile_id>
</talkback>