📄 cc1100.c
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//cc1100 source code packet
#include "cc1100.h"
unsigned char status[2];
unsigned char WaitRxEndtime;
unsigned char PacketLength;
/*****************************************************************************************
config the register of CC1100
Parameter:return 1 means systemerr,return 0 means systemok
*****************************************************************************************/
BYTE CC_WriteRfSettings() //433mhz //4.8k
{
/*CC_SPIWriteReg(CCxxx0_FSCTRL1, 0x06); //data rate:2.4K,433MHZ
CC_SPIWriteReg(CCxxx0_FSCTRL0, 0x00);
CC_SPIWriteReg(CCxxx0_FREQ2, 0x10);
CC_SPIWriteReg(CCxxx0_FREQ1, 0xB0);
CC_SPIWriteReg(CCxxx0_FREQ0, 0x71);
CC_SPIWriteReg(CCxxx0_MDMCFG4, 0xF6);
CC_SPIWriteReg(CCxxx0_MDMCFG3, 0x83);
CC_SPIWriteReg(CCxxx0_MDMCFG2, 0x03);
CC_SPIWriteReg(CCxxx0_MDMCFG1, 0x22);
CC_SPIWriteReg(CCxxx0_MDMCFG0, 0xF8);
CC_SPIWriteReg(CCxxx0_CHANNR, 0x00);
CC_SPIWriteReg(CCxxx0_DEVIATN, 0x15);
CC_SPIWriteReg(CCxxx0_FREND1, 0x56);
CC_SPIWriteReg(CCxxx0_FREND0, 0x10);
CC_SPIWriteReg(CCxxx0_MCSM1, 0x30);
CC_SPIWriteReg(CCxxx0_MCSM0, 0x18);
CC_SPIWriteReg(CCxxx0_FOCCFG, 0x16);
CC_SPIWriteReg(CCxxx0_BSCFG, 0x6C);
CC_SPIWriteReg(CCxxx0_AGCCTRL2, 0x03);
CC_SPIWriteReg(CCxxx0_AGCCTRL0, 0x91);
CC_SPIWriteReg(CCxxx0_FSCAL3, 0xe9);
CC_SPIWriteReg(CCxxx0_FSCAL2, 0x0A);
CC_SPIWriteReg(CCxxx0_FSCAL0, 0x1F);
CC_SPIWriteReg(CCxxx0_FSTEST, 0x59);
CC_SPIWriteReg(CCxxx0_TEST2, 0x81);
CC_SPIWriteReg(CCxxx0_TEST1, 0x35);
CC_SPIWriteReg(CCxxx0_TEST0, 0x09);
CC_SPIWriteReg(CCxxx0_IOCFG2, 0x24);
CC_SPIWriteReg(CCxxx0_IOCFG0, 0x06);
CC_SPIWriteReg(CCxxx0_PKTCTRL1, 0x04);//CRC AUTOFLUSH;ADDRESS CHECK
CC_SPIWriteReg(CCxxx0_PKTCTRL0, 0x05);
CC_SPIWriteReg(CCxxx0_ADDR, 0x00);
CC_SPIWriteReg(CCxxx0_PKTLEN, 0xFF);*/
CC_SPIWriteReg(CCxxx0_FSCTRL1, 0x06); //data rate 4.8K,433M
CC_SPIWriteReg(CCxxx0_FSCTRL0, 0x00);
CC_SPIWriteReg(CCxxx0_FREQ2, 0x10);
CC_SPIWriteReg(CCxxx0_FREQ1, 0xA7);
CC_SPIWriteReg(CCxxx0_FREQ0, 0x62);
CC_SPIWriteReg(CCxxx0_MDMCFG4, 0xC7);
CC_SPIWriteReg(CCxxx0_MDMCFG3, 0x83);
CC_SPIWriteReg(CCxxx0_MDMCFG2, 0x03);
CC_SPIWriteReg(CCxxx0_MDMCFG1, 0x22);
CC_SPIWriteReg(CCxxx0_MDMCFG0, 0xF8);
CC_SPIWriteReg(CCxxx0_CHANNR, 0x00);
CC_SPIWriteReg(CCxxx0_DEVIATN, 0x40);
CC_SPIWriteReg(CCxxx0_FREND1, 0x56);
CC_SPIWriteReg(CCxxx0_FREND0, 0x10);
CC_SPIWriteReg(CCxxx0_MCSM1, 0x30);
CC_SPIWriteReg(CCxxx0_MCSM0, 0x18);
CC_SPIWriteReg(CCxxx0_FOCCFG, 0x16);
CC_SPIWriteReg(CCxxx0_BSCFG, 0x6C);
CC_SPIWriteReg(CCxxx0_AGCCTRL2, 0x43);
CC_SPIWriteReg(CCxxx0_AGCCTRL0, 0x91);
CC_SPIWriteReg(CCxxx0_FSCAL3, 0xe9);
CC_SPIWriteReg(CCxxx0_FSCAL2, 0x2A);
CC_SPIWriteReg(CCxxx0_FSCAL0, 0x1F);
CC_SPIWriteReg(CCxxx0_FSTEST, 0x59);
CC_SPIWriteReg(CCxxx0_TEST2, 0x81);
CC_SPIWriteReg(CCxxx0_TEST1, 0x35);
CC_SPIWriteReg(CCxxx0_TEST0, 0x09);
CC_SPIWriteReg(CCxxx0_IOCFG2, 0x29);
CC_SPIWriteReg(CCxxx0_IOCFG0, 0x06);
CC_SPIWriteReg(CCxxx0_PKTCTRL1, 0x04);//CRC AUTOFLUSH;ADDRESS CHECK
CC_SPIWriteReg(CCxxx0_PKTCTRL0, 0x05);
CC_SPIWriteReg(CCxxx0_ADDR, 0x00);
CC_SPIWriteReg(CCxxx0_PKTLEN, 0xFF);
if(CC_SPIReadReg(CCxxx0_MDMCFG3)!=0x83)
return 1; //err
else
return 0; //no err
}
/***********************************************************************************
延时L毫秒
IN：L
OUT：NONE
************************************************************************************/
void Dly1mS(unsigned int l)
{
int i;
while(l--)
for(i=0;i<255;i++);
}
// Delay function. # of CPU cycles delayed is similar to "cycles". Specifically,
// it's ((cycles-15) % 6) + 15. Not exact, but gives a sense of the real-time
// delay. Also, if MCLK ~1MHz, "cycles" is similar to # of useconds delayed.
void CC_Wait(unsigned int cycles)
{
while(cycles>15) // 15 cycles consumed by overhead
cycles = cycles - 6; // 6 cycles consumed each iteration
}
/****************************************************************************
This routine sets up SPI transfer
****************************************************************************/
void CC_SPISetup(void)
{
CC_GDO0_PxDIR &= ~CC_GDO0_PIN;
CC_GDO2_PxDIR &= ~CC_GDO2_PIN;
P2REN |= CC_GDO0_PIN+CC_GDO2_PIN;
P2OUT |= CC_GDO0_PIN+CC_GDO2_PIN;
P3REN |= CC_SPI_USCIB0_SOMI;
P3OUT |= CC_SPI_USCIB0_SOMI;
CC_CSn_PxOUT |= CC_CSn_PIN;
CC_CSn_PxDIR |= CC_CSn_PIN; // /CS disable
UCB0CTL1 = UCSWRST;
UCB0CTL1 = UCSWRST | UCSSEL1;
UCB0CTL0 = UCCKPH | UCMSB | UCMST | UCSYNC;
UCB0BR0 = 2;
UCB0BR1 = 0;
CC_SPI_USCIB0_PxSEL |= CC_SPI_USCIB0_SIMO | CC_SPI_USCIB0_SOMI | CC_SPI_USCIB0_UCLK;
// SPI option select
CC_SPI_USCIB0_PxDIR |= CC_SPI_USCIB0_SIMO | CC_SPI_USCIB0_UCLK;
// SPI TXD out direction
UCB0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
}
void CC_SPIWriteReg(BYTE addr, BYTE value)
{
CC_CSn_PxOUT &= ~CC_CSn_PIN; // /CS enable
while (CC_SPI_USCIB0_PxIN&CC_SPI_USCIB0_SOMI);// Wait for CCxxxx ready
addr&=0x7F;
IFG2 &= ~UCB0RXIFG; // Clear flag
UCB0TXBUF = addr; // Send address
while (!(IFG2&UCB0RXIFG)); // Wait for TX to finish
IFG2 &= ~UCB0RXIFG; // Clear flag
UCB0TXBUF = value; // Send data
while (!(IFG2&UCB0RXIFG)); // Wait for TX to finish
CC_CSn_PxOUT |= CC_CSn_PIN; // /CS disable
}
void CC_SPIWriteBurstReg(BYTE addr, BYTE *buffer, BYTE count)
{
unsigned int i;
CC_CSn_PxOUT &= ~CC_CSn_PIN; // /CS enable
while (CC_SPI_USCIB0_PxIN&CC_SPI_USCIB0_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCB0RXIFG;
UCB0TXBUF = addr | CC_WRITE_BURST;// Send address
while (!(IFG2&UCB0RXIFG)); // Wait for TX to finish
for (i = 0; i < count; i++)
{
IFG2 &= ~UCB0RXIFG;
UCB0TXBUF = buffer[i]; // Send data
while (!(IFG2&UCB0RXIFG)); // Wait for TX to finish
}
CC_CSn_PxOUT |= CC_CSn_PIN; // /CS disable
}
BYTE CC_SPIReadReg(BYTE addr)
{
BYTE x;
CC_CSn_PxOUT &= ~CC_CSn_PIN; // /CS enable
while (CC_SPI_USCIB0_PxIN&CC_SPI_USCIB0_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCB0RXIFG; // Clear flag
UCB0TXBUF = (addr | CC_READ_SINGLE);// Send address
while (!(IFG2&UCB0RXIFG)); // Wait for TX to finish
IFG2 &= ~UCB0RXIFG; //
UCB0TXBUF = 0; // Dummy write so we can read data
// Address is now being TX'ed, with dummy byte waiting in TXBUF...
while (!(IFG2&UCB0RXIFG)); // Wait for RX to finish
x = UCB0RXBUF; // Read data
CC_CSn_PxOUT |= CC_CSn_PIN; // /CS disable
return x;
}
void CC_SPIReadBurstReg(BYTE addr, BYTE *buffer, BYTE count)
{
BYTE i;
CC_CSn_PxOUT &= ~CC_CSn_PIN; // /CS enable
while (CC_SPI_USCIB0_PxIN&CC_SPI_USCIB0_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCB0RXIFG; // Clear flag
UCB0TXBUF = (addr | CC_READ_BURST);// Send address
while (!(IFG2&UCB0RXIFG)); // Wait for TXBUF ready
IFG2 &= ~UCB0RXIFG;
UCB0TXBUF = 0; // Dummy write to read 1st data byte
// Addr byte is now being TX'ed, with dummy byte to follow immediately after
while (!(IFG2&UCB0RXIFG)); // Wait for end of addr byte TX
for (i = 0; i < (count-1); i++)
{
buffer[i] = UCB0RXBUF; // Store data from last data RX
IFG2 &= ~UCB0RXIFG;
UCB0TXBUF = 0; //Initiate next data RX, meanwhile..
while (!(IFG2&UCB0RXIFG)); // Wait for RX to finish
}
buffer[count-1] = UCB0RXBUF; // Store last RX byte in buffer
CC_CSn_PxOUT |= CC_CSn_PIN; // /CS disable
}
BYTE CC_SPIReadStatus(BYTE addr)
{
BYTE x;
CC_CSn_PxOUT &= ~CC_CSn_PIN; // /CS enable
while (CC_SPI_USCIB0_PxIN & CC_SPI_USCIB0_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCB0RXIFG; // Clear flag set during last write
UCB0TXBUF = (addr | CC_READ_BURST);// Send address
while (!(IFG2&UCB0RXIFG)); // Wait for TX to finish
IFG2 &= ~UCB0RXIFG; // Clear flag set during last write
UCB0TXBUF = 0; // Dummy write so we can read data
while (!(IFG2&UCB0RXIFG)); // Wait for RX to finish
x = UCB0RXBUF; // Read data
CC_CSn_PxOUT |= CC_CSn_PIN; // /CS disable
return x;
}
void CC_SPIStrobe(BYTE strobe)
{
CC_CSn_PxOUT &= ~CC_CSn_PIN; // /CS enable
while (CC_SPI_USCIB0_PxIN&CC_SPI_USCIB0_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCB0RXIFG; // Clear flag
UCB0TXBUF = strobe; // Send strobe
// Strobe addr is now being TX'ed
while (!(IFG2&UCB0RXIFG)); // Wait for end of addr TX
CC_CSn_PxOUT |= CC_CSn_PIN; // /CS disable
}
void CC_PowerupReset(void)
{
CC_SPIStrobe(CCxxx0_SIDLE);
CC_CSn_PxOUT |= CC_CSn_PIN;
CC_Wait(30);
CC_CSn_PxOUT &= ~CC_CSn_PIN;
CC_Wait(30);
CC_CSn_PxOUT |= CC_CSn_PIN;
CC_Wait(45);
CC_CSn_PxOUT &= ~CC_CSn_PIN; // /CS enable
while (CC_SPI_USCIB0_PxIN&CC_SPI_USCIB0_SOMI);// Wait for CCxxxx ready
IFG2 &= ~UCB0RXIFG; // Clear flag
UCB0TXBUF = CCxxx0_SRES; // Send strobe
// Strobe addr is now being TX'ed
while (!(IFG2&UCB0RXIFG)); // Wait for end of addr TX
while (CC_SPI_USCIB0_PxIN&CC_SPI_USCIB0_SOMI);
CC_CSn_PxOUT |= CC_CSn_PIN; // /CS disable
}
/*****************************************************************************************
void halRfSendPacket(BYTE *txBuffer, UINT8 size)
发送数据包
ARGUMENTS:
BYTE *txBuffer
Pointer to a buffer containg the data that are going to be transmitted
UINT8 size
The size of the txBuffer
*****************************************************************************************/
BYTE CC_SendPacket(BYTE *txBuffer,BYTE size)
{
BYTE j;
unsigned int i;
CC_SPIStrobe(CCxxx0_SIDLE);
CC_SPIStrobe(CCxxx0_SFTX);
CC_SPIWriteBurstReg(CCxxx0_TXFIFO, txBuffer, size);
Dly1mS(1);
CC_SPIStrobe(CCxxx0_STX);
//WaitRxEndtime=0;
j=size*20;
while(!(CC_GDO0_PxIN&CC_GDO0_PIN)) //Asserts when sync word has been sent/received
{
for(i=0;i<1000;i++); //delay 1ms
j--;
if(j==0)
{
CC_SPIStrobe(CCxxx0_SIDLE);//不发射，退出
return 1;
}
}
j=size*20;
while(CC_GDO0_PxIN&CC_GDO0_PIN) //de-asserts at the end of the packet
{
Dly1mS(1);
j--;
if(!j)
{
CC_SPIStrobe(CCxxx0_SIDLE);
return 1;
}
}
return 0;
}// halRfSendPacket
/*****************************************************************************************
BOOL halRfReceivePacket(BYTE *rxBuffer, UINT8 *length)
接收数据包
ARGUMENTS:
BYTE *rxBuffer
Pointer to the buffer where the incoming data should be stored
UINT8 *length
Pointer to a variable containing the size of the buffer where the incoming data should be
stored. After this function returns, that variable holds the packet length.
RETURN VALUE:
BOOL
TRUE: CRC OK
FALSE: CRC NOT OK
*******************************************************************************************/
BYTE CC_ReceivePacket(BYTE *rxBuffer, UINT8 length)
{
BYTE j;
CC_SPIStrobe(CCxxx0_SRX);
Dly1mS(1);
if(CC_SPIReadStatus(CCxxx0_RXBYTES)==0) return 0;
Dly1mS(2);
j=length*20;
while((CC_SPIReadStatus(CCxxx0_MARCSTATE)&0x1f)!=0x01)
{
Dly1mS(1);
j--;
if(!j)
{
CC_SPIStrobe(CCxxx0_SIDLE);
CC_SPIStrobe(CCxxx0_SFRX);
return 0;
}
}
PacketLength = CC_SPIReadReg(CCxxx0_RXFIFO);
if((PacketLength<0x20) && (PacketLength>0))
{
CC_SPIReadBurstReg(CCxxx0_RXFIFO, rxBuffer, PacketLength);
// Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
CC_SPIReadBurstReg(CCxxx0_RXFIFO, status, 2);
return (status[1] & CC_CRC_OK);
}
else
{
CC_SPIStrobe(CCxxx0_SIDLE);
CC_SPIStrobe(CCxxx0_SFRX);
return 0;
}
}
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