alarm3.vhd

数字钟的VHDL源程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY alarm3 IS
 PORT(settime:      IN STD_LOGIC;
      
      freq_l:     IN STD_LOGIC;
      ALARM:      OUT STD_LOGIC;                         --dirve signal for the bell
      
      hourhdis:   IN INTEGER RANGE 0 TO 2;               --time information recieved from module of "clock"
      hourldis:   IN INTEGER RANGE 0 TO 9;
      minhdis:    IN INTEGER RANGE 0 TO 5;
      minldis:    IN INTEGER RANGE 0 TO 9;
      sechdis:    IN INTEGER RANGE 0 TO 5;
      secldis:    IN INTEGER RANGE 0 TO 9);
 END alarm3;
ARCHITECTURE archi OF alarm3 IS
  SIGNAL seclow,minlow,hourlow: INTEGER RANGE 0 TO 9;
  SIGNAL sechigh,minhigh: INTEGER RANGE 0 TO 5;
  SIGNAL hourhigh: INTEGER RANGE 0 TO 2;
   BEGIN
   PROCESS(secldis)
    BEGIN                              --the clock alarm
    IF settime='1' THEN
            seclow<=secldis;
            sechigh<=sechdis;
            minlow<=minldis;
            minhigh<= minhdis;
            hourlow<=hourldis;
            hourhigh<=hourhdis;
    ELSE
       IF (hourhdis=hourhigh and hourldis=hourlow and minhdis=minhigh and minldis=minlow and sechdis=0 ) or
          (hourhdis=hourhigh and hourldis=hourlow and minhdis=minhigh and minldis=minlow and sechdis=1 ) or
          (hourhdis=hourhigh and hourldis=hourlow and minhdis=minhigh and minldis=minlow and sechdis=2 ) then

                    ALARM<=freq_l;
    ELSE  ALARM<='0';
    END IF;
END IF;
     END PROCESS;
END archi;