freq_ringl.vhd

来自「数字钟的VHDL源程序」· VHDL 代码 · 共 27 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY freq_ringl IS
PORT(clk:IN STD_LOGIC;
     ringl_clk:OUT STD_LOGIC);
END freq_ringl;

ARCHITECTURE freq_arc OF freq_ringl IS
  SIGNAL cnt_500hz:STD_LOGIC;
BEGIN
PROCESS(CLK)
VARIABLE cnt:INTEGER RANGE 0 TO 2;
CONSTANT modu_500hz:INTEGER:=1;
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
  IF cnt=modu_500hz THEN
    cnt:=0;
    cnt_500hz<= NOT cnt_500hz;
    ringl_clk<=cnt_500hz;
  END IF;
  cnt:=cnt+1;
END IF;
END PROCESS;
END freq_arc;