freq.vhd

来自「数字钟的VHDL源程序」· VHDL 代码 · 共 16 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY freq IS
PORT(clk:IN STD_LOGIC;
     dou_clk:IN STD_LOGIC;
     clock_clk:IN STD_LOGIC;
     display_clk:IN STD_LOGIC;
     ring_clk_h:IN STD_LOGIC;
     ring_clk_l:IN STD_LOGIC);
END freq;

ARCHITECTURE freq_arc OF freq IS