control.rpt

数字钟的VHDL源程序

-- Node name is ':40' = 'minlow2' 
-- Equation name is 'minlow2', location is LC3_C1, type is buried.
minlow2  = DFFE( _EQ013, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ013 = !minlow1 &  minlow2
         # !minlow0 &  minlow2
         #  _LC6_C1 &  minlow2
         # !_LC6_C1 &  minlow0 &  minlow1 & !minlow2;

-- Node name is ':39' = 'minlow3' 
-- Equation name is 'minlow3', location is LC7_C1, type is buried.
minlow3  = DFFE( _EQ014, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ014 = !_LC8_C1 &  minlow3
         # !minlow2 &  minlow3
         #  _LC6_C1 &  minlow3
         # !_LC6_C1 &  _LC8_C1 &  minlow2 & !minlow3;

-- Node name is 'minlset0' 
-- Equation name is 'minlset0', type is output 
minlset0 =  minlow0;

-- Node name is 'minlset1' 
-- Equation name is 'minlset1', type is output 
minlset1 =  minlow1;

-- Node name is 'minlset2' 
-- Equation name is 'minlset2', type is output 
minlset2 =  minlow2;

-- Node name is 'minlset3' 
-- Equation name is 'minlset3', type is output 
minlset3 =  minlow3;

-- Node name is ':45' = 'sechigh0' 
-- Equation name is 'sechigh0', location is LC2_B21, type is buried.
sechigh0 = DFFE( _EQ015, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ015 =  _LC2_C15 &  sechigh0
         # !_LC2_C15 & !sechigh0;

-- Node name is ':44' = 'sechigh1' 
-- Equation name is 'sechigh1', location is LC4_B21, type is buried.
sechigh1 = DFFE( _EQ016, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ016 = !sechigh0 &  sechigh1
         #  _LC2_C15 &  sechigh1
         # !_LC2_C15 &  sechigh0 & !sechigh1;

-- Node name is ':43' = 'sechigh2' 
-- Equation name is 'sechigh2', location is LC7_B21, type is buried.
sechigh2 = DFFE( _EQ017, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ017 = !sechigh1 &  sechigh2
         # !sechigh0 &  sechigh2
         #  _LC2_C15 &  sechigh2
         # !_LC2_C15 &  sechigh0 &  sechigh1 & !sechigh2;

-- Node name is 'sechset0' 
-- Equation name is 'sechset0', type is output 
sechset0 =  sechigh0;

-- Node name is 'sechset1' 
-- Equation name is 'sechset1', type is output 
sechset1 =  sechigh1;

-- Node name is 'sechset2' 
-- Equation name is 'sechset2', type is output 
sechset2 =  sechigh2;

-- Node name is ':49' = 'seclow0' 
-- Equation name is 'seclow0', location is LC4_C15, type is buried.
seclow0  = DFFE( _EQ018, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ018 =  _LC6_C15 &  seclow0
         # !_LC6_C15 & !seclow0;

-- Node name is ':48' = 'seclow1' 
-- Equation name is 'seclow1', location is LC1_C15, type is buried.
seclow1  = DFFE( _EQ019, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ019 = !seclow0 &  seclow1
         #  _LC6_C15 &  seclow1
         # !_LC6_C15 &  seclow0 & !seclow1;

-- Node name is ':47' = 'seclow2' 
-- Equation name is 'seclow2', location is LC7_C15, type is buried.
seclow2  = DFFE( _EQ020, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ020 = !seclow1 &  seclow2
         # !seclow0 &  seclow2
         #  _LC6_C15 &  seclow2
         # !_LC6_C15 &  seclow0 &  seclow1 & !seclow2;

-- Node name is ':46' = 'seclow3' 
-- Equation name is 'seclow3', location is LC5_C15, type is buried.
seclow3  = DFFE( _EQ021, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ021 = !_LC8_C15 &  seclow3
         # !seclow2 &  seclow3
         #  _LC6_C15 &  seclow3
         # !_LC6_C15 &  _LC8_C15 &  seclow2 & !seclow3;

-- Node name is 'seclset0' 
-- Equation name is 'seclset0', type is output 
seclset0 =  seclow0;

-- Node name is 'seclset1' 
-- Equation name is 'seclset1', type is output 
seclset1 =  seclow1;

-- Node name is 'seclset2' 
-- Equation name is 'seclset2', type is output 
seclset2 =  seclow2;

-- Node name is 'seclset3' 
-- Equation name is 'seclset3', type is output 
seclset3 =  seclow3;

-- Node name is ':29' = 'setmark' 
-- Equation name is 'setmark', location is LC8_A8, type is buried.
setmark  = DFFE(!setmark, GLOBAL( begend), GLOBAL(!reset),  VCC,  VCC);

-- Node name is 'settime' 
-- Equation name is 'settime', type is output 
settime  =  setmark;

-- Node name is 'weekset0' 
-- Equation name is 'weekset0', type is output 
weekset0 =  week0;

-- Node name is 'weekset1' 
-- Equation name is 'weekset1', type is output 
weekset1 =  week1;

-- Node name is 'weekset2' 
-- Equation name is 'weekset2', type is output 
weekset2 =  week2;

-- Node name is ':52' = 'week0' 
-- Equation name is 'week0', location is LC3_C18, type is buried.
week0    = DFFE( _EQ022, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ022 =  _LC8_C18 &  week0
         # !_LC8_C18 & !week0;

-- Node name is ':51' = 'week1' 
-- Equation name is 'week1', location is LC6_C18, type is buried.
week1    = DFFE( _EQ023, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ023 = !week0 &  week1
         #  _LC8_C18 &  week1
         # !_LC8_C18 &  week0 & !week1;

-- Node name is ':50' = 'week2' 
-- Equation name is 'week2', location is LC2_C18, type is buried.
week2    = DFFE( _EQ024, GLOBAL( keyup), GLOBAL(!reset),  VCC,  VCC);
  _EQ024 = !week1 &  week2
         # !week0 &  week2
         #  _LC8_C18 &  week2
         # !_LC8_C18 &  week0 &  week1 & !week2;

-- Node name is '|LPM_ADD_SUB:270|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C10', type is buried 
_LC7_C10 = LCELL( _EQ025);
  _EQ025 =  hourlow0 &  hourlow1;

-- Node name is '|LPM_ADD_SUB:323|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C1', type is buried 
_LC8_C1  = LCELL( _EQ026);
  _EQ026 =  minlow0 &  minlow1;

-- Node name is '|LPM_ADD_SUB:376|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C15', type is buried 
_LC8_C15 = LCELL( _EQ027);
  _EQ027 =  seclow0 &  seclow1;

-- Node name is '~488~1' 
-- Equation name is '~488~1', location is LC4_C1, type is buried.
-- synthesized logic cell 
!_LC4_C1 = _LC4_C1~NOT;
_LC4_C1~NOT = LCELL( _EQ028);
  _EQ028 = !adjsta~6 & !adjsta~7 & !adjsta~8;

-- Node name is '~488~2' 
-- Equation name is '~488~2', location is LC3_C15, type is buried.
-- synthesized logic cell 
!_LC3_C15 = _LC3_C15~NOT;
_LC3_C15~NOT = LCELL( _EQ029);
  _EQ029 = !adjsta~5 & !_LC4_C1;

-- Node name is '~488~3' 
-- Equation name is '~488~3', location is LC8_C18, type is buried.
-- synthesized logic cell 
!_LC8_C18 = _LC8_C18~NOT;
_LC8_C18~NOT = LCELL( _EQ030);
  _EQ030 =  adjsta~2 & !adjsta~3 & !adjsta~4 & !_LC3_C15;

-- Node name is '~584~1' 
-- Equation name is '~584~1', location is LC6_C15, type is buried.
-- synthesized logic cell 
!_LC6_C15 = _LC6_C15~NOT;
_LC6_C15~NOT = LCELL( _EQ031);
  _EQ031 =  adjsta~3 & !adjsta~4 & !adjsta~5 & !_LC4_C1;

-- Node name is '~656~1' 
-- Equation name is '~656~1', location is LC2_C15, type is buried.
-- synthesized logic cell 
!_LC2_C15 = _LC2_C15~NOT;
_LC2_C15~NOT = LCELL( _EQ032);
  _EQ032 =  adjsta~4 & !adjsta~5 & !_LC4_C1;

-- Node name is '~752~1' 
-- Equation name is '~752~1', location is LC6_C1, type is buried.
-- synthesized logic cell 
!_LC6_C1 = _LC6_C1~NOT;
_LC6_C1~NOT = LCELL( _EQ033);
  _EQ033 =  adjsta~5 & !adjsta~6 & !adjsta~7 & !adjsta~8;

-- Node name is '~824~1' 
-- Equation name is '~824~1', location is LC2_C1, type is buried.
-- synthesized logic cell 
!_LC2_C1 = _LC2_C1~NOT;
_LC2_C1~NOT = LCELL( _EQ034);
  _EQ034 =  adjsta~6 & !adjsta~7 & !adjsta~8;

-- Node name is '~920~1' 
-- Equation name is '~920~1', location is LC6_C10, type is buried.
-- synthesized logic cell 
!_LC6_C10 = _LC6_C10~NOT;
_LC6_C10~NOT = LCELL( _EQ035);
  _EQ035 =  adjsta~7 & !adjsta~8;



Project Information                               c:\clock3\clock2\control.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:02
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,389K