📄 control.rpt
字号:
14 - - B -- OUTPUT 0 1 0 0 minhset2
77 - - - 01 OUTPUT 0 1 0 0 minlset0
56 - - C -- OUTPUT 0 1 0 0 minlset1
57 - - C -- OUTPUT 0 1 0 0 minlset2
55 - - C -- OUTPUT 0 1 0 0 minlset3
64 - - B -- OUTPUT 0 1 0 0 sechset0
63 - - B -- OUTPUT 0 1 0 0 sechset1
16 - - B -- OUTPUT 0 1 0 0 sechset2
33 - - - 15 OUTPUT 0 1 0 0 seclset0
19 - - C -- OUTPUT 0 1 0 0 seclset1
23 - - C -- OUTPUT 0 1 0 0 seclset2
22 - - C -- OUTPUT 0 1 0 0 seclset3
69 - - A -- OUTPUT 0 1 0 0 settime
30 - - - 18 OUTPUT 0 1 0 0 weekset0
31 - - - 17 OUTPUT 0 1 0 0 weekset1
70 - - A -- OUTPUT 0 1 0 0 weekset2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\clock3\clock2\control.rpt
control
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - C 18 DFFE + 0 0 0 1 adjsta~1
- 7 - C 18 DFFE + 0 1 0 2 adjsta~2
- 1 - C 18 DFFE + 0 1 0 3 adjsta~3
- 1 - C 20 DFFE + 0 1 0 4 adjsta~4
- 2 - C 20 DFFE + 0 1 0 5 adjsta~5
- 4 - C 10 DFFE + 0 1 0 4 adjsta~6
- 5 - C 10 DFFE + 0 1 0 5 adjsta~7
- 4 - C 18 DFFE + 0 2 0 7 adjsta~8
- 7 - C 10 AND2 0 2 0 1 |LPM_ADD_SUB:270|addcore:adder|:59
- 8 - C 01 AND2 0 2 0 1 |LPM_ADD_SUB:323|addcore:adder|:59
- 8 - C 15 AND2 0 2 0 1 |LPM_ADD_SUB:376|addcore:adder|:59
- 8 - A 08 DFFE + 0 0 1 0 setmark (:29)
- 1 - A 14 DFFE + 0 2 1 0 hourhigh1 (:30)
- 7 - A 14 DFFE + 0 1 1 1 hourhigh0 (:31)
- 3 - C 10 DFFE + 0 3 1 0 hourlow3 (:32)
- 2 - C 10 DFFE + 0 3 1 1 hourlow2 (:33)
- 8 - C 10 DFFE + 0 2 1 2 hourlow1 (:34)
- 1 - C 10 DFFE + 0 1 1 3 hourlow0 (:35)
- 3 - B 19 DFFE + 0 3 1 0 minhigh2 (:36)
- 1 - B 19 DFFE + 0 2 1 1 minhigh1 (:37)
- 5 - B 19 DFFE + 0 1 1 2 minhigh0 (:38)
- 7 - C 01 DFFE + 0 3 1 0 minlow3 (:39)
- 3 - C 01 DFFE + 0 3 1 1 minlow2 (:40)
- 5 - C 01 DFFE + 0 2 1 2 minlow1 (:41)
- 1 - C 01 DFFE + 0 1 1 3 minlow0 (:42)
- 7 - B 21 DFFE + 0 3 1 0 sechigh2 (:43)
- 4 - B 21 DFFE + 0 2 1 1 sechigh1 (:44)
- 2 - B 21 DFFE + 0 1 1 2 sechigh0 (:45)
- 5 - C 15 DFFE + 0 3 1 0 seclow3 (:46)
- 7 - C 15 DFFE + 0 3 1 1 seclow2 (:47)
- 1 - C 15 DFFE + 0 2 1 2 seclow1 (:48)
- 4 - C 15 DFFE + 0 1 1 3 seclow0 (:49)
- 2 - C 18 DFFE + 0 3 1 0 week2 (:50)
- 6 - C 18 DFFE + 0 2 1 1 week1 (:51)
- 3 - C 18 DFFE + 0 1 1 2 week0 (:52)
- 4 - C 01 AND2 s ! 0 3 0 3 ~488~1
- 3 - C 15 AND2 s ! 0 2 0 1 ~488~2
- 8 - C 18 AND2 s ! 0 4 0 3 ~488~3
- 6 - C 15 AND2 s ! 0 4 0 4 ~584~1
- 2 - C 15 AND2 s ! 0 3 0 3 ~656~1
- 6 - C 01 AND2 s ! 0 4 0 4 ~752~1
- 2 - C 01 AND2 s ! 0 3 0 3 ~824~1
- 6 - C 10 AND2 s ! 0 2 0 4 ~920~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\clock3\clock2\control.rpt
control
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 1/ 48( 2%) 2/ 48( 4%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 3/ 96( 3%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
C: 8/ 96( 8%) 4/ 48( 8%) 5/ 48( 10%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\clock3\clock2\control.rpt
control
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 23 keyup
INPUT 8 enter
INPUT 1 begend
Device-Specific Information: c:\clock3\clock2\control.rpt
control
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 32 reset
Device-Specific Information: c:\clock3\clock2\control.rpt
control
** EQUATIONS **
begend : INPUT;
enter : INPUT;
keyup : INPUT;
reset : INPUT;
-- Node name is 'adjsta~1'
-- Equation name is 'adjsta~1', location is LC5_C18, type is buried.
adjsta~1 = DFFE( VCC, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjsta~2'
-- Equation name is 'adjsta~2', location is LC7_C18, type is buried.
adjsta~2 = DFFE(!adjsta~1, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjsta~3'
-- Equation name is 'adjsta~3', location is LC1_C18, type is buried.
adjsta~3 = DFFE( adjsta~4, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjsta~4'
-- Equation name is 'adjsta~4', location is LC1_C20, type is buried.
adjsta~4 = DFFE( adjsta~5, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjsta~5'
-- Equation name is 'adjsta~5', location is LC2_C20, type is buried.
adjsta~5 = DFFE( adjsta~6, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjsta~6'
-- Equation name is 'adjsta~6', location is LC4_C10, type is buried.
adjsta~6 = DFFE( adjsta~7, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjsta~7'
-- Equation name is 'adjsta~7', location is LC5_C10, type is buried.
adjsta~7 = DFFE( adjsta~8, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
-- Node name is 'adjsta~8'
-- Equation name is 'adjsta~8', location is LC4_C18, type is buried.
adjsta~8 = DFFE( _EQ001, GLOBAL( enter), GLOBAL(!reset), VCC, VCC);
_EQ001 = adjsta~3
# adjsta~2;
-- Node name is ':31' = 'hourhigh0'
-- Equation name is 'hourhigh0', location is LC7_A14, type is buried.
hourhigh0 = DFFE( _EQ002, GLOBAL( keyup), GLOBAL(!reset), VCC, VCC);
_EQ002 = !adjsta~8 & hourhigh0
# adjsta~8 & !hourhigh0;
-- Node name is ':30' = 'hourhigh1'
-- Equation name is 'hourhigh1', location is LC1_A14, type is buried.
hourhigh1 = DFFE( _EQ003, GLOBAL( keyup), GLOBAL(!reset), VCC, VCC);
_EQ003 = !hourhigh0 & hourhigh1
# !adjsta~8 & hourhigh1
# adjsta~8 & hourhigh0 & !hourhigh1;
-- Node name is 'hourhset0'
-- Equation name is 'hourhset0', type is output
hourhset0 = hourhigh0;
-- Node name is 'hourhset1'
-- Equation name is 'hourhset1', type is output
hourhset1 = hourhigh1;
-- Node name is ':35' = 'hourlow0'
-- Equation name is 'hourlow0', location is LC1_C10, type is buried.
hourlow0 = DFFE( _EQ004, GLOBAL( keyup), GLOBAL(!reset), VCC, VCC);
_EQ004 = hourlow0 & _LC6_C10
# !hourlow0 & !_LC6_C10;
-- Node name is ':34' = 'hourlow1'
-- Equation name is 'hourlow1', location is LC8_C10, type is buried.
hourlow1 = DFFE( _EQ005, GLOBAL( keyup), GLOBAL(!reset), VCC, VCC);
_EQ005 = !hourlow0 & hourlow1
# hourlow1 & _LC6_C10
# hourlow0 & !hourlow1 & !_LC6_C10;
-- Node name is ':33' = 'hourlow2'
-- Equation name is 'hourlow2', location is LC2_C10, type is buried.
hourlow2 = DFFE( _EQ006, GLOBAL( keyup), GLOBAL(!reset), VCC, VCC);
_EQ006 = !hourlow1 & hourlow2
# !hourlow0 & hourlow2
# hourlow2 & _LC6_C10
# hourlow0 & hourlow1 & !hourlow2 & !_LC6_C10;
-- Node name is ':32' = 'hourlow3'
-- Equation name is 'hourlow3', location is LC3_C10, type is buried.
hourlow3 = DFFE( _EQ007, GLOBAL( keyup), GLOBAL(!reset), VCC, VCC);
_EQ007 = hourlow3 & !_LC7_C10
# !hourlow2 & hourlow3
# hourlow3 & _LC6_C10
# hourlow2 & !hourlow3 & !_LC6_C10 & _LC7_C10;
-- Node name is 'hourlset0'
-- Equation name is 'hourlset0', type is output
hourlset0 = hourlow0;
-- Node name is 'hourlset1'
-- Equation name is 'hourlset1', type is output
hourlset1 = hourlow1;
-- Node name is 'hourlset2'
-- Equation name is 'hourlset2', type is output
hourlset2 = hourlow2;
-- Node name is 'hourlset3'
-- Equation name is 'hourlset3', type is output
hourlset3 = hourlow3;
-- Node name is ':38' = 'minhigh0'
-- Equation name is 'minhigh0', location is LC5_B19, type is buried.
minhigh0 = DFFE( _EQ008, GLOBAL( keyup), GLOBAL(!reset), VCC, VCC);
_EQ008 = _LC2_C1 & minhigh0
# !_LC2_C1 & !minhigh0;
-- Node name is ':37' = 'minhigh1'
-- Equation name is 'minhigh1', location is LC1_B19, type is buried.
minhigh1 = DFFE( _EQ009, GLOBAL( keyup), GLOBAL(!reset), VCC, VCC);
_EQ009 = !minhigh0 & minhigh1
# _LC2_C1 & minhigh1
# !_LC2_C1 & minhigh0 & !minhigh1;
-- Node name is ':36' = 'minhigh2'
-- Equation name is 'minhigh2', location is LC3_B19, type is buried.
minhigh2 = DFFE( _EQ010, GLOBAL( keyup), GLOBAL(!reset), VCC, VCC);
_EQ010 = !minhigh1 & minhigh2
# !minhigh0 & minhigh2
# _LC2_C1 & minhigh2
# !_LC2_C1 & minhigh0 & minhigh1 & !minhigh2;
-- Node name is 'minhset0'
-- Equation name is 'minhset0', type is output
minhset0 = minhigh0;
-- Node name is 'minhset1'
-- Equation name is 'minhset1', type is output
minhset1 = minhigh1;
-- Node name is 'minhset2'
-- Equation name is 'minhset2', type is output
minhset2 = minhigh2;
-- Node name is ':42' = 'minlow0'
-- Equation name is 'minlow0', location is LC1_C1, type is buried.
minlow0 = DFFE( _EQ011, GLOBAL( keyup), GLOBAL(!reset), VCC, VCC);
_EQ011 = _LC6_C1 & minlow0
# !_LC6_C1 & !minlow0;
-- Node name is ':41' = 'minlow1'
-- Equation name is 'minlow1', location is LC5_C1, type is buried.
minlow1 = DFFE( _EQ012, GLOBAL( keyup), GLOBAL(!reset), VCC, VCC);
_EQ012 = !minlow0 & minlow1
# _LC6_C1 & minlow1
# !_LC6_C1 & minlow0 & !minlow1;
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