📄 control2.rpt
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Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------- LC4 adjsta~1
| +------------- LC8 hourhset0
| | +----------- LC6 hourhset1
| | | +--------- LC3 minhset1
| | | | +------- LC11 minhset2
| | | | | +----- LC5 sechset1
| | | | | | +--- LC7 sechset2
| | | | | | | +- LC10 settime
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'A'
LC | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC4 -> * * * * * * * - | * * | <-- adjsta~1
LC8 -> - * * - - - - - | * - | <-- hourhset0
LC3 -> - - - * * - - - | * - | <-- minhset1
LC5 -> - - - - - * * - | * - | <-- sechset1
Pin
5 -> - - - - - - - * | * - | <-- begend
43 -> - - - - - - - - | - - | <-- enter
2 -> - - - - - - - - | - - | <-- keyup
4 -> * * * * * * * * | * * | <-- reset
LC20 -> - * * * * * * - | * * | <-- adjsta~2
LC25 -> - * * * * * * - | * * | <-- adjsta~3
LC17 -> - - - * * - - - | * - | <-- minhset0
LC23 -> - - - - - * * - | * - | <-- sechset0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\clock2\control2.rpt
control2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC20 adjsta~2
| +----------------------------- LC25 adjsta~3
| | +--------------------------- LC27 hourlset0
| | | +------------------------- LC28 hourlset1
| | | | +----------------------- LC29 hourlset2
| | | | | +--------------------- LC31 hourlset3
| | | | | | +------------------- LC17 minhset0
| | | | | | | +----------------- LC18 minlset0
| | | | | | | | +--------------- LC19 minlset1
| | | | | | | | | +------------- LC21 minlset2
| | | | | | | | | | +----------- LC30 minlset3
| | | | | | | | | | | +--------- LC23 sechset0
| | | | | | | | | | | | +------- LC26 seclset0
| | | | | | | | | | | | | +----- LC24 seclset1
| | | | | | | | | | | | | | +--- LC22 seclset2
| | | | | | | | | | | | | | | +- LC32 seclset3
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC20 -> * * * * * * * * * * * * * * * * | * * | <-- adjsta~2
LC25 -> * * * * * * * * * * * * * * * * | * * | <-- adjsta~3
LC27 -> - - * * * * - - - - - - - - - - | - * | <-- hourlset0
LC28 -> - - - * * * - - - - - - - - - - | - * | <-- hourlset1
LC29 -> - - - - * * - - - - - - - - - - | - * | <-- hourlset2
LC18 -> - - - - - - - * * * * - - - - - | - * | <-- minlset0
LC19 -> - - - - - - - - * * * - - - - - | - * | <-- minlset1
LC21 -> - - - - - - - - - * * - - - - - | - * | <-- minlset2
LC26 -> - - - - - - - - - - - - * * * * | - * | <-- seclset0
LC24 -> - - - - - - - - - - - - - * * * | - * | <-- seclset1
LC22 -> - - - - - - - - - - - - - - * * | - * | <-- seclset2
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- enter
2 -> - - - - - - - - - - - - - - - - | - - | <-- keyup
4 -> * * * * * * * * * * * * * * * * | * * | <-- reset
LC4 -> * * * * * * * * * * * * * * * * | * * | <-- adjsta~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\clock2\control2.rpt
control2
** EQUATIONS **
begend : INPUT;
enter : INPUT;
keyup : INPUT;
reset : INPUT;
-- Node name is 'adjsta~1'
-- Equation name is 'adjsta~1', location is LC004, type is buried.
adjsta~1 = TFFE(!_EQ001, GLOBAL( enter), !reset, VCC, VCC);
_EQ001 = !adjsta~1 & reset;
-- Node name is 'adjsta~2'
-- Equation name is 'adjsta~2', location is LC020, type is buried.
adjsta~2 = DFFE( _EQ002 $ GND, GLOBAL( enter), !reset, VCC, VCC);
_EQ002 = !adjsta~1 & !adjsta~2 & adjsta~3 & !reset
# adjsta~1 & !adjsta~3 & !reset;
-- Node name is 'adjsta~3'
-- Equation name is 'adjsta~3', location is LC025, type is buried.
adjsta~3 = DFFE( _EQ003 $ GND, GLOBAL( enter), !reset, VCC, VCC);
_EQ003 = !adjsta~1 & adjsta~2 & adjsta~3 & !reset
# adjsta~1 & !adjsta~2 & !reset;
-- Node name is 'hourhset0' = 'hourhigh0'
-- Equation name is 'hourhset0', location is LC008, type is output.
hourhset0 = TFFE( _EQ004, GLOBAL( keyup), !reset, VCC, VCC);
_EQ004 = adjsta~1 & !adjsta~2 & !adjsta~3;
-- Node name is 'hourhset1' = 'hourhigh1'
-- Equation name is 'hourhset1', location is LC006, type is output.
hourhset1 = TFFE( _EQ005, GLOBAL( keyup), !reset, VCC, VCC);
_EQ005 = adjsta~1 & !adjsta~2 & !adjsta~3 & hourhset0;
-- Node name is 'hourlset0' = 'hourlow0'
-- Equation name is 'hourlset0', location is LC027, type is output.
hourlset0 = TFFE( _EQ006, GLOBAL( keyup), !reset, VCC, VCC);
_EQ006 = !adjsta~1 & adjsta~2 & adjsta~3;
-- Node name is 'hourlset1' = 'hourlow1'
-- Equation name is 'hourlset1', location is LC028, type is output.
hourlset1 = TFFE( _EQ007, GLOBAL( keyup), !reset, VCC, VCC);
_EQ007 = !adjsta~1 & adjsta~2 & adjsta~3 & hourlset0;
-- Node name is 'hourlset2' = 'hourlow2'
-- Equation name is 'hourlset2', location is LC029, type is output.
hourlset2 = TFFE( _EQ008, GLOBAL( keyup), !reset, VCC, VCC);
_EQ008 = !adjsta~1 & adjsta~2 & adjsta~3 & hourlset0 & hourlset1;
-- Node name is 'hourlset3' = 'hourlow3'
-- Equation name is 'hourlset3', location is LC031, type is output.
hourlset3 = TFFE( _EQ009, GLOBAL( keyup), !reset, VCC, VCC);
_EQ009 = !adjsta~1 & adjsta~2 & adjsta~3 & hourlset0 & hourlset1 &
hourlset2;
-- Node name is 'minhset0' = 'minhigh0'
-- Equation name is 'minhset0', location is LC017, type is output.
minhset0 = TFFE( _EQ010, GLOBAL( keyup), !reset, VCC, VCC);
_EQ010 = adjsta~1 & !adjsta~2 & adjsta~3;
-- Node name is 'minhset1' = 'minhigh1'
-- Equation name is 'minhset1', location is LC003, type is output.
minhset1 = TFFE( _EQ011, GLOBAL( keyup), !reset, VCC, VCC);
_EQ011 = adjsta~1 & !adjsta~2 & adjsta~3 & minhset0;
-- Node name is 'minhset2' = 'minhigh2'
-- Equation name is 'minhset2', location is LC011, type is output.
minhset2 = TFFE( _EQ012, GLOBAL( keyup), !reset, VCC, VCC);
_EQ012 = adjsta~1 & !adjsta~2 & adjsta~3 & minhset0 & minhset1;
-- Node name is 'minlset0' = 'minlow0'
-- Equation name is 'minlset0', location is LC018, type is output.
minlset0 = TFFE( _EQ013, GLOBAL( keyup), !reset, VCC, VCC);
_EQ013 = !adjsta~1 & !adjsta~2 & adjsta~3;
-- Node name is 'minlset1' = 'minlow1'
-- Equation name is 'minlset1', location is LC019, type is output.
minlset1 = TFFE( _EQ014, GLOBAL( keyup), !reset, VCC, VCC);
_EQ014 = !adjsta~1 & !adjsta~2 & adjsta~3 & minlset0;
-- Node name is 'minlset2' = 'minlow2'
-- Equation name is 'minlset2', location is LC021, type is output.
minlset2 = TFFE( _EQ015, GLOBAL( keyup), !reset, VCC, VCC);
_EQ015 = !adjsta~1 & !adjsta~2 & adjsta~3 & minlset0 & minlset1;
-- Node name is 'minlset3' = 'minlow3'
-- Equation name is 'minlset3', location is LC030, type is output.
minlset3 = TFFE( _EQ016, GLOBAL( keyup), !reset, VCC, VCC);
_EQ016 = !adjsta~1 & !adjsta~2 & adjsta~3 & minlset0 & minlset1 &
minlset2;
-- Node name is 'sechset0' = 'sechigh0'
-- Equation name is 'sechset0', location is LC023, type is output.
sechset0 = TFFE( _EQ017, GLOBAL( keyup), !reset, VCC, VCC);
_EQ017 = adjsta~1 & adjsta~2 & !adjsta~3;
-- Node name is 'sechset1' = 'sechigh1'
-- Equation name is 'sechset1', location is LC005, type is output.
sechset1 = TFFE( _EQ018, GLOBAL( keyup), !reset, VCC, VCC);
_EQ018 = adjsta~1 & adjsta~2 & !adjsta~3 & sechset0;
-- Node name is 'sechset2' = 'sechigh2'
-- Equation name is 'sechset2', location is LC007, type is output.
sechset2 = TFFE( _EQ019, GLOBAL( keyup), !reset, VCC, VCC);
_EQ019 = adjsta~1 & adjsta~2 & !adjsta~3 & sechset0 & sechset1;
-- Node name is 'seclset0' = 'seclow0'
-- Equation name is 'seclset0', location is LC026, type is output.
seclset0 = TFFE( _EQ020, GLOBAL( keyup), !reset, VCC, VCC);
_EQ020 = !adjsta~1 & adjsta~2 & !adjsta~3;
-- Node name is 'seclset1' = 'seclow1'
-- Equation name is 'seclset1', location is LC024, type is output.
seclset1 = TFFE( _EQ021, GLOBAL( keyup), !reset, VCC, VCC);
_EQ021 = !adjsta~1 & adjsta~2 & !adjsta~3 & seclset0;
-- Node name is 'seclset2' = 'seclow2'
-- Equation name is 'seclset2', location is LC022, type is output.
seclset2 = TFFE( _EQ022, GLOBAL( keyup), !reset, VCC, VCC);
_EQ022 = !adjsta~1 & adjsta~2 & !adjsta~3 & seclset0 & seclset1;
-- Node name is 'seclset3' = 'seclow3'
-- Equation name is 'seclset3', location is LC032, type is output.
seclset3 = TFFE( _EQ023, GLOBAL( keyup), !reset, VCC, VCC);
_EQ023 = !adjsta~1 & adjsta~2 & !adjsta~3 & seclset0 & seclset1 &
seclset2;
-- Node name is 'settime'
-- Equation name is 'settime', location is LC010, type is output.
settime = LCELL( _EQ024 $ begend);
_EQ024 = begend & reset;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\clock2\control2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,517K
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