mux2.rpt

数字钟的VHDL源程序

        | | | | | +------------------- LC61 hourldis3
        | | | | | | +----------------- LC62 minhdis0
        | | | | | | | +--------------- LC53 minhdis1
        | | | | | | | | +------------- LC58 minhdis2
        | | | | | | | | | +----------- LC55 minldis0
        | | | | | | | | | | +--------- LC49 minldis1
        | | | | | | | | | | | +------- LC50 minldis2
        | | | | | | | | | | | | +----- LC51 minldis3
        | | | | | | | | | | | | | +--- LC52 sechdis0
        | | | | | | | | | | | | | | +- LC54 sechdis1
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':

Pin
31   -> * - - - - - - - - - - - - - - | - - - * | <-- a00
39   -> - * - - - - - - - - - - - - - | - - - * | <-- a01
37   -> - - * - - - - - - - - - - - - | - - - * | <-- a10
34   -> - - - * - - - - - - - - - - - | - - - * | <-- a11
33   -> - - - - * - - - - - - - - - - | - - - * | <-- a12
36   -> - - - - - * - - - - - - - - - | - - - * | <-- a13
41   -> - - - - - - * - - - - - - - - | - - - * | <-- a20
45   -> - - - - - - - * - - - - - - - | - - - * | <-- a21
44   -> - - - - - - - - * - - - - - - | - - - * | <-- a22
25   -> - - - - - - - - - * - - - - - | - - - * | <-- a30
29   -> - - - - - - - - - - * - - - - | - - - * | <-- a31
28   -> - - - - - - - - - - - * - - - | - - - * | <-- a32
24   -> - - - - - - - - - - - - * - - | - - - * | <-- a33
1    -> - - - - - - - - - - - - - * - | - - - * | <-- a40
83   -> - - - - - - - - - - - - - - * | - - - * | <-- a41
50   -> * - - - - - - - - - - - - - - | - - - * | <-- b00
49   -> - * - - - - - - - - - - - - - | - - - * | <-- b01
27   -> - - * - - - - - - - - - - - - | - - - * | <-- b10
30   -> - - - * - - - - - - - - - - - | - - - * | <-- b11
12   -> - - - - * - - - - - - - - - - | - - - * | <-- b12
15   -> - - - - - * - - - - - - - - - | - - - * | <-- b13
16   -> - - - - - - * - - - - - - - - | - - - * | <-- b20
17   -> - - - - - - - * - - - - - - - | - - - * | <-- b21
18   -> - - - - - - - - * - - - - - - | - - - * | <-- b22
20   -> - - - - - - - - - * - - - - - | - - - * | <-- b30
21   -> - - - - - - - - - - * - - - - | - - - * | <-- b31
11   -> - - - - - - - - - - - * - - - | - - - * | <-- b32
10   -> - - - - - - - - - - - - * - - | - - - * | <-- b33
9    -> - - - - - - - - - - - - - * - | - - - * | <-- b40
8    -> - - - - - - - - - - - - - - * | - - - * | <-- b41
22   -> * * * * * * * * * * * * * * * | - - * * | <-- sel


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                d:\clock2\mux2.rpt
mux2

** EQUATIONS **

a00      : INPUT;
a01      : INPUT;
a10      : INPUT;
a11      : INPUT;
a12      : INPUT;
a13      : INPUT;
a20      : INPUT;
a21      : INPUT;
a22      : INPUT;
a30      : INPUT;
a31      : INPUT;
a32      : INPUT;
a33      : INPUT;
a40      : INPUT;
a41      : INPUT;
a42      : INPUT;
a50      : INPUT;
a51      : INPUT;
a52      : INPUT;
a53      : INPUT;
b00      : INPUT;
b01      : INPUT;
b10      : INPUT;
b11      : INPUT;
b12      : INPUT;
b13      : INPUT;
b20      : INPUT;
b21      : INPUT;
b22      : INPUT;
b30      : INPUT;
b31      : INPUT;
b32      : INPUT;
b33      : INPUT;
b40      : INPUT;
b41      : INPUT;
b42      : INPUT;
b50      : INPUT;
b51      : INPUT;
b52      : INPUT;
b53      : INPUT;
sel      : INPUT;

-- Node name is 'hourhdis0' 
-- Equation name is 'hourhdis0', location is LC057, type is output.
 hourhdis0 = LCELL( _EQ001 $  GND);
  _EQ001 =  b00 &  sel
         #  a00 & !sel;

-- Node name is 'hourhdis1' 
-- Equation name is 'hourhdis1', location is LC064, type is output.
 hourhdis1 = LCELL( _EQ002 $  GND);
  _EQ002 =  b01 &  sel
         #  a01 & !sel;

-- Node name is 'hourldis0' 
-- Equation name is 'hourldis0', location is LC063, type is output.
 hourldis0 = LCELL( _EQ003 $  GND);
  _EQ003 =  b10 &  sel
         #  a10 & !sel;

-- Node name is 'hourldis1' 
-- Equation name is 'hourldis1', location is LC060, type is output.
 hourldis1 = LCELL( _EQ004 $  GND);
  _EQ004 =  b11 &  sel
         #  a11 & !sel;

-- Node name is 'hourldis2' 
-- Equation name is 'hourldis2', location is LC059, type is output.
 hourldis2 = LCELL( _EQ005 $  GND);
  _EQ005 =  b12 &  sel
         #  a12 & !sel;

-- Node name is 'hourldis3' 
-- Equation name is 'hourldis3', location is LC061, type is output.
 hourldis3 = LCELL( _EQ006 $  GND);
  _EQ006 =  b13 &  sel
         #  a13 & !sel;

-- Node name is 'minhdis0' 
-- Equation name is 'minhdis0', location is LC062, type is output.
 minhdis0 = LCELL( _EQ007 $  GND);
  _EQ007 =  b20 &  sel
         #  a20 & !sel;

-- Node name is 'minhdis1' 
-- Equation name is 'minhdis1', location is LC053, type is output.
 minhdis1 = LCELL( _EQ008 $  GND);
  _EQ008 =  b21 &  sel
         #  a21 & !sel;

-- Node name is 'minhdis2' 
-- Equation name is 'minhdis2', location is LC058, type is output.
 minhdis2 = LCELL( _EQ009 $  GND);
  _EQ009 =  b22 &  sel
         #  a22 & !sel;

-- Node name is 'minldis0' 
-- Equation name is 'minldis0', location is LC055, type is output.
 minldis0 = LCELL( _EQ010 $  GND);
  _EQ010 =  b30 &  sel
         #  a30 & !sel;

-- Node name is 'minldis1' 
-- Equation name is 'minldis1', location is LC049, type is output.
 minldis1 = LCELL( _EQ011 $  GND);
  _EQ011 =  b31 &  sel
         #  a31 & !sel;

-- Node name is 'minldis2' 
-- Equation name is 'minldis2', location is LC050, type is output.
 minldis2 = LCELL( _EQ012 $  GND);
  _EQ012 =  b32 &  sel
         #  a32 & !sel;

-- Node name is 'minldis3' 
-- Equation name is 'minldis3', location is LC051, type is output.
 minldis3 = LCELL( _EQ013 $  GND);
  _EQ013 =  b33 &  sel
         #  a33 & !sel;

-- Node name is 'sechdis0' 
-- Equation name is 'sechdis0', location is LC052, type is output.
 sechdis0 = LCELL( _EQ014 $  GND);
  _EQ014 =  b40 &  sel
         #  a40 & !sel;

-- Node name is 'sechdis1' 
-- Equation name is 'sechdis1', location is LC054, type is output.
 sechdis1 = LCELL( _EQ015 $  GND);
  _EQ015 =  b41 &  sel
         #  a41 & !sel;

-- Node name is 'sechdis2' 
-- Equation name is 'sechdis2', location is LC035, type is output.
 sechdis2 = LCELL( _EQ016 $  GND);
  _EQ016 =  b42 &  sel
         #  a42 & !sel;

-- Node name is 'secldis0' 
-- Equation name is 'secldis0', location is LC036, type is output.
 secldis0 = LCELL( _EQ017 $  GND);
  _EQ017 =  b50 &  sel
         #  a50 & !sel;

-- Node name is 'secldis1' 
-- Equation name is 'secldis1', location is LC039, type is output.
 secldis1 = LCELL( _EQ018 $  GND);
  _EQ018 =  b51 &  sel
         #  a51 & !sel;

-- Node name is 'secldis2' 
-- Equation name is 'secldis2', location is LC040, type is output.
 secldis2 = LCELL( _EQ019 $  GND);
  _EQ019 =  b52 &  sel
         #  a52 & !sel;

-- Node name is 'secldis3' 
-- Equation name is 'secldis3', location is LC043, type is output.
 secldis3 = LCELL( _EQ020 $  GND);
  _EQ020 =  b53 &  sel
         #  a53 & !sel;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                         d:\clock2\mux2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,093K