📄 mux2.rpt
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Project Information d:\clock2\mux2.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/26/2008 13:58:21
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MUX2
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
mux2 EPM7064SLC84-5 41 20 0 20 0 31 %
User Pins: 41 20 0
Device-Specific Information: d:\clock2\mux2.rpt
mux2
***** Logic for device 'mux2' compiled without errors.
Device: EPM7064SLC84-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
Device-Specific Information: d:\clock2\mux2.rpt
mux2
** ERROR SUMMARY **
Info: Chip 'mux2' in device 'EPM7064SLC84-5' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
h h h h h
o o m o o o
u u i u u u
V r r n r r r
C h l h V l l l
C d d d C d d d
b b b b G b b b I G a G a G i i i C i i i
3 3 4 4 N 4 5 5 N N 4 N 4 N s s s I s s s
2 3 0 1 D 2 0 1 T D 0 D 1 D 1 0 0 O 3 1 2
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
b12 | 12 74 | minhdis2
VCCIO | 13 73 | hourhdis0
#TDI | 14 72 | GND
b13 | 15 71 | #TDO
b20 | 16 70 | minldis0
b21 | 17 69 | sechdis1
b22 | 18 68 | minhdis1
GND | 19 67 | sechdis0
b30 | 20 66 | VCCIO
b31 | 21 65 | minldis3
sel | 22 EPM7064SLC84-5 64 | minldis2
#TMS | 23 63 | minldis1
a33 | 24 62 | #TCK
a30 | 25 61 | RESERVED
VCCIO | 26 60 | a42
b10 | 27 59 | GND
a32 | 28 58 | a50
a31 | 29 57 | a51
b11 | 30 56 | secldis3
a00 | 31 55 | a52
GND | 32 54 | a53
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
a a b a a V a b a G V a a s G s b b s s V
1 1 5 1 1 C 0 5 2 N C 2 2 e N e 0 0 e e C
2 1 3 3 0 C 1 2 0 D C 2 1 c D c 1 0 c c C
I I h l l l I
O N d d d d O
T i i i i
s s s s
2 0 1 2
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\clock2\mux2.rpt
mux2
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 16/16(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 16/16(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 5/16( 31%) 15/16( 93%) 0/16( 0%) 11/36( 30%)
D: LC49 - LC64 15/16( 93%) 16/16(100%) 0/16( 0%) 31/36( 86%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 63/64 ( 98%)
Total logic cells used: 20/64 ( 31%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 20/64 ( 31%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 3.00
Total fan-in: 60
Total input pins required: 41
Total fast input logic cells required: 0
Total output pins required: 20
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 20
Total flipflops required: 0
Total product terms required: 40
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: d:\clock2\mux2.rpt
mux2
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
31 (25) (B) INPUT 0 0 0 0 0 1 0 a00
39 (19) (B) INPUT 0 0 0 0 0 1 0 a01
37 (20) (B) INPUT 0 0 0 0 0 1 0 a10
34 (23) (B) INPUT 0 0 0 0 0 1 0 a11
33 (24) (B) INPUT 0 0 0 0 0 1 0 a12
36 (21) (B) INPUT 0 0 0 0 0 1 0 a13
41 (17) (B) INPUT 0 0 0 0 0 1 0 a20
45 (34) (C) INPUT 0 0 0 0 0 1 0 a21
44 (33) (C) INPUT 0 0 0 0 0 1 0 a22
25 (30) (B) INPUT 0 0 0 0 0 1 0 a30
29 (27) (B) INPUT 0 0 0 0 0 1 0 a31
28 (28) (B) INPUT 0 0 0 0 0 1 0 a32
24 (31) (B) INPUT 0 0 0 0 0 1 0 a33
1 - - INPUT 0 0 0 0 0 1 0 a40
83 - - INPUT 0 0 0 0 0 1 0 a41
60 (46) (C) INPUT 0 0 0 0 0 1 0 a42
58 (45) (C) INPUT 0 0 0 0 0 1 0 a50
57 (44) (C) INPUT 0 0 0 0 0 1 0 a51
55 (42) (C) INPUT 0 0 0 0 0 1 0 a52
54 (41) (C) INPUT 0 0 0 0 0 1 0 a53
50 (38) (C) INPUT 0 0 0 0 0 1 0 b00
49 (37) (C) INPUT 0 0 0 0 0 1 0 b01
27 (29) (B) INPUT 0 0 0 0 0 1 0 b10
30 (26) (B) INPUT 0 0 0 0 0 1 0 b11
12 (9) (A) INPUT 0 0 0 0 0 1 0 b12
15 (7) (A) INPUT 0 0 0 0 0 1 0 b13
16 (6) (A) INPUT 0 0 0 0 0 1 0 b20
17 (5) (A) INPUT 0 0 0 0 0 1 0 b21
18 (4) (A) INPUT 0 0 0 0 0 1 0 b22
20 (3) (A) INPUT 0 0 0 0 0 1 0 b30
21 (2) (A) INPUT 0 0 0 0 0 1 0 b31
11 (10) (A) INPUT 0 0 0 0 0 1 0 b32
10 (11) (A) INPUT 0 0 0 0 0 1 0 b33
9 (12) (A) INPUT 0 0 0 0 0 1 0 b40
8 (13) (A) INPUT 0 0 0 0 0 1 0 b41
6 (14) (A) INPUT 0 0 0 0 0 1 0 b42
5 (15) (A) INPUT 0 0 0 0 0 1 0 b50
4 (16) (A) INPUT 0 0 0 0 0 1 0 b51
40 (18) (B) INPUT 0 0 0 0 0 1 0 b52
35 (22) (B) INPUT 0 0 0 0 0 1 0 b53
22 (1) (A) INPUT 0 0 0 0 0 20 0 sel
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\clock2\mux2.rpt
mux2
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
73 57 D OUTPUT t 0 0 0 3 0 0 0 hourhdis0
81 64 D OUTPUT t 0 0 0 3 0 0 0 hourhdis1
80 63 D OUTPUT t 0 0 0 3 0 0 0 hourldis0
76 60 D OUTPUT t 0 0 0 3 0 0 0 hourldis1
75 59 D OUTPUT t 0 0 0 3 0 0 0 hourldis2
77 61 D OUTPUT t 0 0 0 3 0 0 0 hourldis3
79 62 D OUTPUT t 0 0 0 3 0 0 0 minhdis0
68 53 D OUTPUT t 0 0 0 3 0 0 0 minhdis1
74 58 D OUTPUT t 0 0 0 3 0 0 0 minhdis2
70 55 D OUTPUT t 0 0 0 3 0 0 0 minldis0
63 49 D OUTPUT t 0 0 0 3 0 0 0 minldis1
64 50 D OUTPUT t 0 0 0 3 0 0 0 minldis2
65 51 D OUTPUT t 0 0 0 3 0 0 0 minldis3
67 52 D OUTPUT t 0 0 0 3 0 0 0 sechdis0
69 54 D OUTPUT t 0 0 0 3 0 0 0 sechdis1
46 35 C OUTPUT t 0 0 0 3 0 0 0 sechdis2
48 36 C OUTPUT t 0 0 0 3 0 0 0 secldis0
51 39 C OUTPUT t 0 0 0 3 0 0 0 secldis1
52 40 C OUTPUT t 0 0 0 3 0 0 0 secldis2
56 43 C OUTPUT t 0 0 0 3 0 0 0 secldis3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\clock2\mux2.rpt
mux2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------- LC35 sechdis2
| +------- LC36 secldis0
| | +----- LC39 secldis1
| | | +--- LC40 secldis2
| | | | +- LC43 secldis3
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'C'
LC | | | | | | A B C D | Logic cells that feed LAB 'C':
Pin
1 -> - - - - - | - - - * | <-- a40
83 -> - - - - - | - - - * | <-- a41
60 -> * - - - - | - - * - | <-- a42
58 -> - * - - - | - - * - | <-- a50
57 -> - - * - - | - - * - | <-- a51
55 -> - - - * - | - - * - | <-- a52
54 -> - - - - * | - - * - | <-- a53
6 -> * - - - - | - - * - | <-- b42
5 -> - * - - - | - - * - | <-- b50
4 -> - - * - - | - - * - | <-- b51
40 -> - - - * - | - - * - | <-- b52
35 -> - - - - * | - - * - | <-- b53
22 -> * * * * * | - - * * | <-- sel
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\clock2\mux2.rpt
mux2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------------------- LC57 hourhdis0
| +--------------------------- LC64 hourhdis1
| | +------------------------- LC63 hourldis0
| | | +----------------------- LC60 hourldis1
| | | | +--------------------- LC59 hourldis2
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