📄 clock5.rpt
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_EQ017 = minhdis0 & !minhdis1 & minhdis2 & minldis0 & !minldis1 &
!minldis2 & minldis3 & sechdis0 & !sechdis1 & sechdis2 &
secldis0 & !secldis1 & !secldis2 & secldis3;
_EQ018 = !minhset0 & settime;
_EQ019 = minhset0 & settime;
-- Node name is 'minhdis1' = 'minhigh1'
-- Equation name is 'minhdis1', location is LC062, type is output.
minhdis1 = TFFE( _EQ020, GLOBAL( clk), !_EQ021, !_EQ022, VCC);
_EQ020 = minhdis0 & !minhdis1 & minhdis2 & minldis0 & !minldis1 &
!minldis2 & minldis3 & sechdis0 & !sechdis1 & sechdis2 &
secldis0 & !secldis1 & !secldis2 & secldis3 & _X001;
_X001 = EXP( hourldis0 & !hourldis1 & !hourldis2 & hourldis3);
_EQ021 = !minhset1 & settime;
_EQ022 = minhset1 & settime;
-- Node name is 'minhdis2' = 'minhigh2'
-- Equation name is 'minhdis2', location is LC061, type is output.
minhdis2 = TFFE( _EQ023, GLOBAL( clk), !_EQ024, !_EQ025, VCC);
_EQ023 = hourldis0 & !hourldis1 & !hourldis2 & hourldis3 & minhdis0 &
!minhdis1 & minhdis2 & minldis0 & !minldis1 & !minldis2 &
minldis3 & sechdis0 & !sechdis1 & sechdis2 & secldis0 &
!secldis1 & !secldis2 & secldis3;
_EQ024 = !minhset2 & settime;
_EQ025 = minhset2 & settime;
-- Node name is 'minldis0' = 'minlow0'
-- Equation name is 'minldis0', location is LC064, type is output.
minldis0 = TFFE( _EQ026, GLOBAL( clk), !_EQ027, !_EQ028, VCC);
_EQ026 = minldis0 & !minldis1 & !minldis2 & minldis3 & sechdis0 &
!sechdis1 & sechdis2 & secldis0 & !secldis1 & !secldis2 &
secldis3;
_EQ027 = !minlset0 & settime;
_EQ028 = minlset0 & settime;
-- Node name is 'minldis1' = 'minlow1'
-- Equation name is 'minldis1', location is LC051, type is output.
minldis1 = TFFE( _EQ029, GLOBAL( clk), !_EQ030, !_EQ031, VCC);
_EQ029 = minhdis1 & minldis0 & !minldis1 & !minldis2 & minldis3 &
sechdis0 & !sechdis1 & sechdis2 & secldis0 & !secldis1 &
!secldis2 & secldis3
# !minhdis2 & minldis0 & !minldis1 & !minldis2 & minldis3 &
sechdis0 & !sechdis1 & sechdis2 & secldis0 & !secldis1 &
!secldis2 & secldis3
# !minhdis0 & minldis0 & !minldis1 & !minldis2 & minldis3 &
sechdis0 & !sechdis1 & sechdis2 & secldis0 & !secldis1 &
!secldis2 & secldis3;
_EQ030 = !minlset1 & settime;
_EQ031 = minlset1 & settime;
-- Node name is 'minldis2' = 'minlow2'
-- Equation name is 'minldis2', location is LC046, type is output.
minldis2 = TFFE( GND, GLOBAL( clk), !_EQ032, !_EQ033, VCC);
_EQ032 = !minlset2 & settime;
_EQ033 = minlset2 & settime;
-- Node name is 'minldis3' = 'minlow3'
-- Equation name is 'minldis3', location is LC054, type is output.
minldis3 = TFFE( _EQ034, GLOBAL( clk), !_EQ035, !_EQ036, VCC);
_EQ034 = minhdis0 & !minhdis1 & minhdis2 & minldis0 & !minldis1 &
!minldis2 & minldis3 & sechdis0 & !sechdis1 & sechdis2 &
secldis0 & !secldis1 & !secldis2 & secldis3;
_EQ035 = !minlset3 & settime;
_EQ036 = minlset3 & settime;
-- Node name is 'sechdis0' = 'sechigh0'
-- Equation name is 'sechdis0', location is LC037, type is output.
sechdis0 = TFFE( _EQ037, GLOBAL( clk), !_EQ038, !_EQ039, VCC);
_EQ037 = sechdis0 & !sechdis1 & sechdis2 & secldis0 & !secldis1 &
!secldis2 & secldis3;
_EQ038 = !sechset0 & settime;
_EQ039 = sechset0 & settime;
-- Node name is 'sechdis1' = 'sechigh1'
-- Equation name is 'sechdis1', location is LC049, type is output.
sechdis1 = TFFE( _EQ040, GLOBAL( clk), !_EQ041, !_EQ042, VCC);
_EQ040 = sechdis0 & !sechdis1 & sechdis2 & secldis0 & !secldis1 &
!secldis2 & secldis3 & _X002;
_X002 = EXP( minldis0 & !minldis1 & !minldis2 & minldis3);
_EQ041 = !sechset1 & settime;
_EQ042 = sechset1 & settime;
-- Node name is 'sechdis2' = 'sechigh2'
-- Equation name is 'sechdis2', location is LC052, type is output.
sechdis2 = TFFE( _EQ043, GLOBAL( clk), !_EQ044, !_EQ045, VCC);
_EQ043 = minldis0 & !minldis1 & !minldis2 & minldis3 & sechdis0 &
!sechdis1 & sechdis2 & secldis0 & !secldis1 & !secldis2 &
secldis3;
_EQ044 = !sechset2 & settime;
_EQ045 = sechset2 & settime;
-- Node name is 'secldis0' = 'seclow0'
-- Equation name is 'secldis0', location is LC038, type is output.
secldis0 = TFFE( _EQ046, GLOBAL( clk), !_EQ047, !_EQ048, VCC);
_EQ046 = secldis0 & !secldis1 & !secldis2 & secldis3;
_EQ047 = !seclset0 & settime;
_EQ048 = seclset0 & settime;
-- Node name is 'secldis1' = 'seclow1'
-- Equation name is 'secldis1', location is LC040, type is output.
secldis1 = TFFE( _EQ049, GLOBAL( clk), !_EQ050, !_EQ051, VCC);
_EQ049 = sechdis1 & secldis0 & !secldis1 & !secldis2 & secldis3
# !sechdis2 & secldis0 & !secldis1 & !secldis2 & secldis3
# !sechdis0 & secldis0 & !secldis1 & !secldis2 & secldis3;
_EQ050 = !seclset1 & settime;
_EQ051 = seclset1 & settime;
-- Node name is 'secldis2' = 'seclow2'
-- Equation name is 'secldis2', location is LC033, type is output.
secldis2 = TFFE( GND, GLOBAL( clk), !_EQ052, !_EQ053, VCC);
_EQ052 = !seclset2 & settime;
_EQ053 = seclset2 & settime;
-- Node name is 'secldis3' = 'seclow3'
-- Equation name is 'secldis3', location is LC036, type is output.
secldis3 = TFFE( _EQ054, GLOBAL( clk), !_EQ055, !_EQ056, VCC);
_EQ054 = sechdis0 & !sechdis1 & sechdis2 & secldis0 & !secldis1 &
!secldis2 & secldis3;
_EQ055 = !seclset3 & settime;
_EQ056 = seclset3 & settime;
-- Node name is 'weekdis0'
-- Equation name is 'weekdis0', location is LC048, type is output.
weekdis0 = LCELL( _EQ057 $ GND);
_EQ057 = settime & weekset0
# _LC042 & !settime;
-- Node name is 'weekdis1'
-- Equation name is 'weekdis1', location is LC035, type is output.
weekdis1 = LCELL( _EQ058 $ GND);
_EQ058 = settime & weekset1
# _LC039 & !settime;
-- Node name is 'weekdis2'
-- Equation name is 'weekdis2', location is LC043, type is output.
weekdis2 = LCELL( _EQ059 $ GND);
_EQ059 = settime & weekset2
# _LC047 & !settime;
-- Node name is '~1298~1'
-- Equation name is '~1298~1', location is LC047, type is buried.
-- synthesized logic cell
_LC047 = LCELL( _EQ060 $ GND);
_EQ060 = settime & weekset2
# _LC047 & !settime
# _LC047 & weekset2;
-- Node name is '~1304~1'
-- Equation name is '~1304~1', location is LC039, type is buried.
-- synthesized logic cell
_LC039 = LCELL( _EQ061 $ GND);
_EQ061 = settime & weekset1
# _LC039 & !settime
# _LC039 & weekset1;
-- Node name is '~1310~1'
-- Equation name is '~1310~1', location is LC042, type is buried.
-- synthesized logic cell
_LC042 = LCELL( _EQ062 $ GND);
_EQ062 = settime & weekset0
# _LC042 & !settime
# _LC042 & weekset0;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\clock2\clock5.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 8,071K
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