📄 clock5.rpt
字号:
59 57 D FF + t 0 0 0 2 19 0 0 hourhdis1 (:67)
60 59 D FF + t 0 0 0 2 18 6 0 hourldis0 (:66)
55 53 D FF + t 0 0 0 2 18 6 0 hourldis1 (:65)
44 41 C FF + t 0 0 0 2 0 6 0 hourldis2 (:64)
47 45 C FF + t 0 0 0 2 0 6 0 hourldis3 (:63)
57 56 D FF + t 0 0 0 2 14 9 0 minhdis0 (:62)
64 62 D FF + t 1 0 0 2 18 9 0 minhdis1 (:61)
62 61 D FF + t 0 0 0 2 18 9 0 minhdis2 (:60)
65 64 D FF + t 0 0 0 2 11 12 0 minldis0 (:59)
52 51 D FF + t 1 0 1 2 14 12 0 minldis1 (:58)
49 46 C FF + t 0 0 0 2 0 12 0 minldis2 (:57)
56 54 D FF + t 0 0 0 2 14 12 0 minldis3 (:56)
40 37 C FF + t 0 0 0 2 7 15 0 sechdis0 (:55)
51 49 D FF + t 1 0 0 2 11 15 0 sechdis1 (:54)
54 52 D FF + t 0 0 0 2 11 15 0 sechdis2 (:53)
41 38 C FF + t 0 0 0 2 4 16 0 secldis0 (:52)
42 40 C FF + t 1 0 1 2 7 16 0 secldis1 (:51)
36 33 C FF + t 0 0 0 2 0 16 0 secldis2 (:50)
39 36 C FF + t 0 0 0 2 7 16 0 secldis3 (:49)
50 48 C OUTPUT t 0 0 0 2 1 0 0 weekdis0
37 35 C OUTPUT t 0 0 0 2 1 0 0 weekdis1
45 43 C OUTPUT t 0 0 0 2 1 0 0 weekdis2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\clock2\clock5.rpt
clock5
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 47 C LCELL s t 0 0 0 2 1 1 1 ~1298~1
- 39 C LCELL s t 0 0 0 2 1 1 1 ~1304~1
- 42 C LCELL s t 0 0 0 2 1 1 1 ~1310~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\clock2\clock5.rpt
clock5
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------------------- LC41 hourldis2
| +------------------------- LC45 hourldis3
| | +----------------------- LC46 minldis2
| | | +--------------------- LC37 sechdis0
| | | | +------------------- LC38 secldis0
| | | | | +----------------- LC40 secldis1
| | | | | | +--------------- LC33 secldis2
| | | | | | | +------------- LC36 secldis3
| | | | | | | | +----------- LC48 weekdis0
| | | | | | | | | +--------- LC35 weekdis1
| | | | | | | | | | +------- LC43 weekdis2
| | | | | | | | | | | +----- LC47 ~1298~1
| | | | | | | | | | | | +--- LC39 ~1304~1
| | | | | | | | | | | | | +- LC42 ~1310~1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC37 -> - - - * - * - * - - - - - - | - - * * | <-- sechdis0
LC38 -> - - - * * * - * - - - - - - | - - * * | <-- secldis0
LC40 -> - - - * * * - * - - - - - - | - - * * | <-- secldis1
LC33 -> - - - * * * * * - - - - - - | - - * * | <-- secldis2
LC36 -> - - - * * * - * - - - - - - | - - * * | <-- secldis3
LC47 -> - - - - - - - - - - * * - - | - - * - | <-- ~1298~1
LC39 -> - - - - - - - - - * - - * - | - - * - | <-- ~1304~1
LC42 -> - - - - - - - - * - - - - * | - - * - | <-- ~1310~1
Pin
67 -> - - - - - - - - - - - - - - | - - - - | <-- clk
68 -> - - - - - - - - - - - - - - | - - - * | <-- hourlset1
46 -> * - - - - - - - - - - - - - | - - * - | <-- hourlset2
23 -> - * - - - - - - - - - - - - | - - * - | <-- hourlset3
12 -> - - * - - - - - - - - - - - | - - * - | <-- minlset2
9 -> - - - * - - - - - - - - - - | - - * - | <-- sechset0
5 -> - - - - * - - - - - - - - - | - - * - | <-- seclset0
4 -> - - - - - * - - - - - - - - | - - * - | <-- seclset1
32 -> - - - - - - * - - - - - - - | - - * - | <-- seclset2
30 -> - - - - - - - * - - - - - - | - - * - | <-- seclset3
18 -> * * * * * * * * * * * * * * | - - * * | <-- settime
29 -> - - - - - - - - * - - - - * | - - * - | <-- weekset0
28 -> - - - - - - - - - * - - * - | - - * - | <-- weekset1
27 -> - - - - - - - - - - * * - - | - - * - | <-- weekset2
LC49 -> - - - * - * - * - - - - - - | - - * * | <-- sechdis1
LC52 -> - - - * - * - * - - - - - - | - - * * | <-- sechdis2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\clock2\clock5.rpt
clock5
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------------- LC60 hourhdis0
| +--------------------- LC57 hourhdis1
| | +------------------- LC59 hourldis0
| | | +----------------- LC53 hourldis1
| | | | +--------------- LC56 minhdis0
| | | | | +------------- LC62 minhdis1
| | | | | | +----------- LC61 minhdis2
| | | | | | | +--------- LC64 minldis0
| | | | | | | | +------- LC51 minldis1
| | | | | | | | | +----- LC54 minldis3
| | | | | | | | | | +--- LC49 sechdis1
| | | | | | | | | | | +- LC52 sechdis2
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC60 -> * * - - - - - - - - - - | - - - * | <-- hourhdis0
LC59 -> * * * * - * * - - - - - | - - - * | <-- hourldis0
LC53 -> * * * * - * * - - - - - | - - - * | <-- hourldis1
LC56 -> * * * * * * * - * * - - | - - - * | <-- minhdis0
LC62 -> * * * * * * * - * * - - | - - - * | <-- minhdis1
LC61 -> * * * * * * * - * * - - | - - - * | <-- minhdis2
LC64 -> * * * * * * * * * * * * | - - - * | <-- minldis0
LC51 -> * * * * * * * * * * * * | - - - * | <-- minldis1
LC54 -> * * * * * * * * * * * * | - - - * | <-- minldis3
LC49 -> * * * * * * * * * * * * | - - * * | <-- sechdis1
LC52 -> * * * * * * * * * * * * | - - * * | <-- sechdis2
Pin
67 -> - - - - - - - - - - - - | - - - - | <-- clk
33 -> * - - - - - - - - - - - | - - - * | <-- hourhset0
24 -> - * - - - - - - - - - - | - - - * | <-- hourhset1
22 -> - - * - - - - - - - - - | - - - * | <-- hourlset0
68 -> - - - * - - - - - - - - | - - - * | <-- hourlset1
25 -> - - - - * - - - - - - - | - - - * | <-- minhset0
17 -> - - - - - * - - - - - - | - - - * | <-- minhset1
15 -> - - - - - - * - - - - - | - - - * | <-- minhset2
14 -> - - - - - - - * - - - - | - - - * | <-- minlset0
13 -> - - - - - - - - * - - - | - - - * | <-- minlset1
10 -> - - - - - - - - - * - - | - - - * | <-- minlset3
8 -> - - - - - - - - - - * - | - - - * | <-- sechset1
7 -> - - - - - - - - - - - * | - - - * | <-- sechset2
18 -> * * * * * * * * * * * * | - - * * | <-- settime
LC41 -> * * * * - * * - - - - - | - - - * | <-- hourldis2
LC45 -> * * * * - * * - - - - - | - - - * | <-- hourldis3
LC46 -> * * * * * * * * * * * * | - - - * | <-- minldis2
LC37 -> * * * * * * * * * * * * | - - * * | <-- sechdis0
LC38 -> * * * * * * * * * * * * | - - * * | <-- secldis0
LC40 -> * * * * * * * * * * * * | - - * * | <-- secldis1
LC33 -> * * * * * * * * * * * * | - - * * | <-- secldis2
LC36 -> * * * * * * * * * * * * | - - * * | <-- secldis3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\clock2\clock5.rpt
clock5
** EQUATIONS **
clk : INPUT;
hourhset0 : INPUT;
hourhset1 : INPUT;
hourlset0 : INPUT;
hourlset1 : INPUT;
hourlset2 : INPUT;
hourlset3 : INPUT;
minhset0 : INPUT;
minhset1 : INPUT;
minhset2 : INPUT;
minlset0 : INPUT;
minlset1 : INPUT;
minlset2 : INPUT;
minlset3 : INPUT;
sechset0 : INPUT;
sechset1 : INPUT;
sechset2 : INPUT;
seclset0 : INPUT;
seclset1 : INPUT;
seclset2 : INPUT;
seclset3 : INPUT;
settime : INPUT;
weekset0 : INPUT;
weekset1 : INPUT;
weekset2 : INPUT;
-- Node name is 'hourhdis0' = 'hourhigh0'
-- Equation name is 'hourhdis0', location is LC060, type is output.
hourhdis0 = TFFE( _EQ001, GLOBAL( clk), !_EQ002, !_EQ003, VCC);
_EQ001 = hourldis0 & !hourldis1 & !hourldis2 & hourldis3 & minhdis0 &
!minhdis1 & minhdis2 & minldis0 & !minldis1 & !minldis2 &
minldis3 & sechdis0 & !sechdis1 & sechdis2 & secldis0 &
!secldis1 & !secldis2 & secldis3;
_EQ002 = !hourhset0 & settime;
_EQ003 = hourhset0 & settime;
-- Node name is 'hourhdis1' = 'hourhigh1'
-- Equation name is 'hourhdis1', location is LC057, type is output.
hourhdis1 = TFFE( _EQ004, GLOBAL( clk), !_EQ005, !_EQ006, VCC);
_EQ004 = hourhdis0 & hourldis0 & !hourldis1 & !hourldis2 & hourldis3 &
minhdis0 & !minhdis1 & minhdis2 & minldis0 & !minldis1 &
!minldis2 & minldis3 & sechdis0 & !sechdis1 & sechdis2 &
secldis0 & !secldis1 & !secldis2 & secldis3;
_EQ005 = !hourhset1 & settime;
_EQ006 = hourhset1 & settime;
-- Node name is 'hourldis0' = 'hourlow0'
-- Equation name is 'hourldis0', location is LC059, type is output.
hourldis0 = TFFE( _EQ007, GLOBAL( clk), !_EQ008, !_EQ009, VCC);
_EQ007 = hourldis0 & !hourldis1 & !hourldis2 & hourldis3 & minhdis0 &
!minhdis1 & minhdis2 & minldis0 & !minldis1 & !minldis2 &
minldis3 & sechdis0 & !sechdis1 & sechdis2 & secldis0 &
!secldis1 & !secldis2 & secldis3;
_EQ008 = !hourlset0 & settime;
_EQ009 = hourlset0 & settime;
-- Node name is 'hourldis1' = 'hourlow1'
-- Equation name is 'hourldis1', location is LC053, type is output.
hourldis1 = TFFE( _EQ010, GLOBAL( clk), !_EQ011, !_EQ012, VCC);
_EQ010 = hourldis0 & !hourldis1 & !hourldis2 & hourldis3 & minhdis0 &
!minhdis1 & minhdis2 & minldis0 & !minldis1 & !minldis2 &
minldis3 & sechdis0 & !sechdis1 & sechdis2 & secldis0 &
!secldis1 & !secldis2 & secldis3;
_EQ011 = !hourlset1 & settime;
_EQ012 = hourlset1 & settime;
-- Node name is 'hourldis2' = 'hourlow2'
-- Equation name is 'hourldis2', location is LC041, type is output.
hourldis2 = TFFE( GND, GLOBAL( clk), !_EQ013, !_EQ014, VCC);
_EQ013 = !hourlset2 & settime;
_EQ014 = hourlset2 & settime;
-- Node name is 'hourldis3' = 'hourlow3'
-- Equation name is 'hourldis3', location is LC045, type is output.
hourldis3 = TFFE( GND, GLOBAL( clk), !_EQ015, !_EQ016, VCC);
_EQ015 = !hourlset3 & settime;
_EQ016 = hourlset3 & settime;
-- Node name is 'minhdis0' = 'minhigh0'
-- Equation name is 'minhdis0', location is LC056, type is output.
minhdis0 = TFFE( _EQ017, GLOBAL( clk), !_EQ018, !_EQ019, VCC);
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