📄 clock5.rpt
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Project Information d:\clock2\clock5.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/28/2008 16:04:26
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
CLOCK5
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
clock5 EPM7064LC68-7 25 23 0 26 2 40 %
User Pins: 25 23 0
Project Information d:\clock2\clock5.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information d:\clock2\clock5.rpt
** FILE HIERARCHY **
|lpm_add_sub:331|
|lpm_add_sub:331|addcore:adder|
|lpm_add_sub:331|addcore:adder|addcore:adder0|
|lpm_add_sub:331|altshift:result_ext_latency_ffs|
|lpm_add_sub:331|altshift:carry_ext_latency_ffs|
|lpm_add_sub:331|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:380|
|lpm_add_sub:380|addcore:adder|
|lpm_add_sub:380|addcore:adder|addcore:adder0|
|lpm_add_sub:380|altshift:result_ext_latency_ffs|
|lpm_add_sub:380|altshift:carry_ext_latency_ffs|
|lpm_add_sub:380|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:454|
|lpm_add_sub:454|addcore:adder|
|lpm_add_sub:454|addcore:adder|addcore:adder0|
|lpm_add_sub:454|altshift:result_ext_latency_ffs|
|lpm_add_sub:454|altshift:carry_ext_latency_ffs|
|lpm_add_sub:454|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:550|
|lpm_add_sub:550|addcore:adder|
|lpm_add_sub:550|addcore:adder|addcore:adder0|
|lpm_add_sub:550|altshift:result_ext_latency_ffs|
|lpm_add_sub:550|altshift:carry_ext_latency_ffs|
|lpm_add_sub:550|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:673|
|lpm_add_sub:673|addcore:adder|
|lpm_add_sub:673|addcore:adder|addcore:adder0|
|lpm_add_sub:673|altshift:result_ext_latency_ffs|
|lpm_add_sub:673|altshift:carry_ext_latency_ffs|
|lpm_add_sub:673|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:818|
|lpm_add_sub:818|addcore:adder|
|lpm_add_sub:818|addcore:adder|addcore:adder0|
|lpm_add_sub:818|altshift:result_ext_latency_ffs|
|lpm_add_sub:818|altshift:carry_ext_latency_ffs|
|lpm_add_sub:818|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\clock2\clock5.rpt
clock5
***** Logic for device 'clock5' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: d:\clock2\clock5.rpt
clock5
** ERROR SUMMARY **
Info: Chip 'clock5' in device 'EPM7064LC68-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
h h
s s s s s o m m m o
e e e e e u i i i u
c c c c c V r n n n r
h h h l l C l l h V h h
s s s s s C s d d C d d
e e e G e e I G G e c G i i C i i
t t t N t t N N N t l N s s I s s
0 1 2 D 0 1 T D D 1 k D 0 1 O 2 0
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
minlset3 | 10 60 | hourldis0
VCCIO | 11 59 | hourhdis1
minlset2 | 12 58 | GND
minlset1 | 13 57 | minhdis0
minlset0 | 14 56 | minldis3
minhset2 | 15 55 | hourldis1
GND | 16 54 | sechdis2
minhset1 | 17 53 | VCCIO
settime | 18 EPM7064LC68-7 52 | minldis1
RESERVED | 19 51 | sechdis1
RESERVED | 20 50 | weekdis0
VCCIO | 21 49 | minldis2
hourlset0 | 22 48 | GND
hourlset3 | 23 47 | hourldis3
hourhset1 | 24 46 | hourlset2
minhset0 | 25 45 | weekdis2
GND | 26 44 | hourldis2
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
w w w s V s h G V s w G s s s s V
e e e e C e o N C e e N e e e e C
e e e c C c u D C c e D c c c c C
k k k l I l r I l k l h l l I
s s s s O s h N d d d d d d O
e e e e e s T i i i i i i
t t t t t e s s s s s s
2 1 0 3 2 t 2 1 3 0 0 1
0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\clock2\clock5.rpt
clock5
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 10/12( 83%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 14/16( 87%) 12/12(100%) 1/16( 6%) 22/36( 61%)
D: LC49 - LC64 12/16( 75%) 12/12(100%) 3/16( 18%) 32/36( 88%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 46/48 ( 95%)
Total logic cells used: 26/64 ( 40%)
Total shareable expanders used: 2/64 ( 3%)
Total Turbo logic cells used: 26/64 ( 40%)
Total shareable expanders not available (n/a): 2/64 ( 3%)
Average fan-in: 11.26
Total fan-in: 293
Total input pins required: 25
Total output pins required: 23
Total bidirectional pins required: 0
Total logic cells required: 26
Total flipflops required: 20
Total product terms required: 81
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 2
Synthesized logic cells: 3/ 64 ( 4%)
Device-Specific Information: d:\clock2\clock5.rpt
clock5
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
67 - - INPUT G 0 0 0 0 0 0 0 clk
33 (17) (B) INPUT 0 0 0 0 0 1 0 hourhset0
24 (27) (B) INPUT 0 0 0 0 0 1 0 hourhset1
22 (29) (B) INPUT 0 0 0 0 0 1 0 hourlset0
68 - - INPUT 0 0 0 0 0 1 0 hourlset1
46 (44) (C) INPUT 0 0 0 0 0 1 0 hourlset2
23 (28) (B) INPUT 0 0 0 0 0 1 0 hourlset3
25 (25) (B) INPUT 0 0 0 0 0 1 0 minhset0
17 (3) (A) INPUT 0 0 0 0 0 1 0 minhset1
15 (4) (A) INPUT 0 0 0 0 0 1 0 minhset2
14 (5) (A) INPUT 0 0 0 0 0 1 0 minlset0
13 (6) (A) INPUT 0 0 0 0 0 1 0 minlset1
12 (8) (A) INPUT 0 0 0 0 0 1 0 minlset2
10 (9) (A) INPUT 0 0 0 0 0 1 0 minlset3
9 (11) (A) INPUT 0 0 0 0 0 1 0 sechset0
8 (12) (A) INPUT 0 0 0 0 0 1 0 sechset1
7 (13) (A) INPUT 0 0 0 0 0 1 0 sechset2
5 (14) (A) INPUT 0 0 0 0 0 1 0 seclset0
4 (16) (A) INPUT 0 0 0 0 0 1 0 seclset1
32 (19) (B) INPUT 0 0 0 0 0 1 0 seclset2
30 (20) (B) INPUT 0 0 0 0 0 1 0 seclset3
18 (1) (A) INPUT 0 0 0 0 0 23 3 settime
29 (21) (B) INPUT 0 0 0 0 0 1 1 weekset0
28 (22) (B) INPUT 0 0 0 0 0 1 1 weekset1
27 (24) (B) INPUT 0 0 0 0 0 1 1 weekset2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\clock2\clock5.rpt
clock5
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
61 60 D FF + t 0 0 0 2 18 1 0 hourhdis0 (:68)
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