📄 display5.rpt
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!minldis3 & _X016 & _X021 & _X022 & _X023 & _X024 & _X025 &
_X026 & _X027 & _X028
# !CURSTA0 & !CURSTA1 & CURSTA2 & !minldis0 & !minldis1 & minldis2 &
!minldis3 & _X016 & _X021 & _X022 & _X023 & _X024 & _X025 &
_X026 & _X027 & _X028
# CURSTA0 & !CURSTA1 & CURSTA2 & sechdis0 & sechdis1 & sechdis2 &
_X016 & _X021 & _X022 & _X023 & _X024 & _X025 & _X026 &
_X027 & _X028;
_X016 = EXP( CURSTA0 & CURSTA1 & !CURSTA2);
_X021 = EXP(!CURSTA2 & secldis0 & !secldis1 & !secldis2 & !secldis3);
_X022 = EXP( CURSTA0 & !CURSTA1 & CURSTA2 & sechdis0 & !sechdis1 & !sechdis2);
_X023 = EXP( CURSTA0 & !CURSTA1 & CURSTA2 & !sechdis0 & !sechdis1 & sechdis2);
_X024 = EXP( CURSTA1 & secldis0 & secldis1 & secldis2 & !secldis3);
_X025 = EXP(!CURSTA2 & secldis0 & secldis1 & secldis2 & !secldis3);
_X026 = EXP( CURSTA1 & secldis0 & !secldis1 & !secldis2 & !secldis3);
_X027 = EXP( CURSTA1 & !secldis0 & !secldis1 & secldis2 & !secldis3);
_X028 = EXP(!CURSTA2 & !secldis0 & !secldis1 & secldis2 & !secldis3);
_EQ044 = _X016 & _X021 & _X022 & _X023 & _X024 & _X025 & _X026 &
_X027 & _X028;
_X016 = EXP( CURSTA0 & CURSTA1 & !CURSTA2);
_X021 = EXP(!CURSTA2 & secldis0 & !secldis1 & !secldis2 & !secldis3);
_X022 = EXP( CURSTA0 & !CURSTA1 & CURSTA2 & sechdis0 & !sechdis1 & !sechdis2);
_X023 = EXP( CURSTA0 & !CURSTA1 & CURSTA2 & !sechdis0 & !sechdis1 & sechdis2);
_X024 = EXP( CURSTA1 & secldis0 & secldis1 & secldis2 & !secldis3);
_X025 = EXP(!CURSTA2 & secldis0 & secldis1 & secldis2 & !secldis3);
_X026 = EXP( CURSTA1 & secldis0 & !secldis1 & !secldis2 & !secldis3);
_X027 = EXP( CURSTA1 & !secldis0 & !secldis1 & secldis2 & !secldis3);
_X028 = EXP(!CURSTA2 & !secldis0 & !secldis1 & secldis2 & !secldis3);
-- Node name is '~4381~1'
-- Equation name is '~4381~1', location is LC043, type is buried.
-- synthesized logic cell
_LC043 = LCELL( _EQ045 $ VCC);
_EQ045 = !CURSTA0 & CURSTA1 & !CURSTA2 & !_LC052 & _X003 & _X019
# !hourhdis1 & !_LC027 & !_LC052 & !_LC064 & _X015 & _X019
# CURSTA0 & !CURSTA1 & !CURSTA2 & !hourhdis1 & _X015
# !_LC027 & !_LC064 & _X002 & _X003;
_X003 = EXP( CURSTA0 & !CURSTA1 & !CURSTA2);
_X019 = EXP(!hourldis0 & !hourldis1 & !hourldis2 & !hourldis3);
_X015 = EXP(!hourhdis0 & !hourhdis1);
_X002 = EXP(!CURSTA0 & CURSTA1 & !CURSTA2);
-- Node name is '~4402~1'
-- Equation name is '~4402~1', location is LC056, type is buried.
-- synthesized logic cell
_LC056 = LCELL( _EQ046 $ _EQ047);
_EQ046 = !CURSTA0 & !hourldis0 & hourldis1 & !hourldis2 & !hourldis3 &
!_LC057 & !_LC058 & !minhdis0 & minhdis1 & !minhdis2 &
!minldis0 & minldis1 & !minldis2 & !minldis3 & !secldis0 &
secldis1 & !secldis2 & !secldis3 & _X003 & _X029 & _X030
# CURSTA0 & !hourldis0 & hourldis1 & !hourldis2 & !hourldis3 &
!_LC057 & !_LC058 & !minhdis0 & minhdis1 & !minhdis2 &
!sechdis0 & sechdis1 & !sechdis2 & !secldis0 & secldis1 &
!secldis2 & !secldis3 & _X003 & _X029 & _X030
# !CURSTA0 & !hourhdis0 & hourhdis1 & !_LC057 & !_LC058 & !minhdis0 &
minhdis1 & !minhdis2 & !minldis0 & minldis1 & !minldis2 &
!minldis3 & !secldis0 & secldis1 & !secldis2 & !secldis3 &
_X002 & _X029 & _X030
# CURSTA0 & !hourhdis0 & hourhdis1 & !_LC057 & !_LC058 & !minhdis0 &
minhdis1 & !minhdis2 & !sechdis0 & sechdis1 & !sechdis2 &
!secldis0 & secldis1 & !secldis2 & !secldis3 & _X002 & _X029 &
_X030;
_X003 = EXP( CURSTA0 & !CURSTA1 & !CURSTA2);
_X029 = EXP(!CURSTA0 & CURSTA1 & !CURSTA2 & !hourldis0 & hourldis1 &
!hourldis2 & !hourldis3 & !_LC038);
_X030 = EXP( CURSTA0 & !CURSTA1 & !CURSTA2 & !hourhdis0 & hourhdis1);
_X002 = EXP(!CURSTA0 & CURSTA1 & !CURSTA2);
_EQ047 = !_LC057 & !_LC058 & _X029 & _X030;
_X029 = EXP(!CURSTA0 & CURSTA1 & !CURSTA2 & !hourldis0 & hourldis1 &
!hourldis2 & !hourldis3 & !_LC038);
_X030 = EXP( CURSTA0 & !CURSTA1 & !CURSTA2 & !hourhdis0 & hourhdis1);
-- Node name is '~4402~2'
-- Equation name is '~4402~2', location is LC057, type is buried.
-- synthesized logic cell
_LC057 = LCELL( _EQ048 $ GND);
_EQ048 = !CURSTA0 & !CURSTA1 & CURSTA2 & !_LC035 & !_LC038 & !minldis0 &
minldis1 & !minldis2 & !minldis3
# !CURSTA0 & !CURSTA1 & CURSTA2 & !_LC035 & !_LC038 & !minldis0 &
minldis1 & !minldis2 & !minldis3
# !CURSTA0 & !CURSTA1 & CURSTA2 & !_LC035 & !_LC038 & !minldis0 &
minldis1 & !minldis2 & !minldis3
# CURSTA0 & !CURSTA1 & CURSTA2 & !_LC035 & !_LC038 & !sechdis0 &
sechdis1 & !sechdis2
# CURSTA0 & !CURSTA1 & CURSTA2 & !_LC035 & !_LC038 & !sechdis0 &
sechdis1 & !sechdis2;
-- Node name is '~4402~3'
-- Equation name is '~4402~3', location is LC058, type is buried.
-- synthesized logic cell
_LC058 = LCELL( _EQ049 $ GND);
_EQ049 = CURSTA0 & CURSTA1 & !CURSTA2 & !_LC035 & !_LC038 & !minhdis0 &
minhdis1 & !minhdis2
# !CURSTA0 & CURSTA1 & !_LC035 & !_LC038 & !secldis0 & secldis1 &
!secldis2 & !secldis3
# CURSTA1 & CURSTA2 & !_LC035 & !_LC038 & !secldis0 & secldis1 &
!secldis2 & !secldis3
# !CURSTA0 & !CURSTA2 & !_LC035 & !_LC038 & !secldis0 & secldis1 &
!secldis2 & !secldis3
# !CURSTA1 & !CURSTA2 & !_LC035 & !_LC038 & !secldis0 & secldis1 &
!secldis2 & !secldis3;
-- Node name is '~4418~1'
-- Equation name is '~4418~1', location is LC059, type is buried.
-- synthesized logic cell
_LC059 = LCELL( _EQ050 $ GND);
_EQ050 = CURSTA0 & CURSTA1 & !CURSTA2 & minhdis0 & minhdis1
# CURSTA0 & CURSTA1 & !CURSTA2 & !minhdis0 & !minhdis1
# CURSTA0 & CURSTA1 & !CURSTA2 & !minhdis2;
-- Node name is '~4419~1'
-- Equation name is '~4419~1', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ051 $ _EQ052);
_EQ051 = !CURSTA0 & !CURSTA1 & CURSTA2 & minldis0 & !minldis1 & minldis2 &
!minldis3 & _X016 & _X031 & _X032 & _X033 & _X034
# !CURSTA0 & !CURSTA1 & CURSTA2 & !minldis0 & minldis1 & minldis2 &
!minldis3 & _X016 & _X031 & _X032 & _X033 & _X034
# CURSTA0 & !CURSTA1 & CURSTA2 & sechdis0 & !sechdis1 & sechdis2 &
_X016 & _X031 & _X032 & _X033 & _X034
# CURSTA0 & !CURSTA1 & CURSTA2 & !sechdis0 & sechdis1 & sechdis2 &
_X016 & _X031 & _X032 & _X033 & _X034;
_X016 = EXP( CURSTA0 & CURSTA1 & !CURSTA2);
_X031 = EXP( CURSTA1 & secldis0 & !secldis1 & secldis2 & !secldis3);
_X032 = EXP( CURSTA1 & !secldis0 & secldis1 & secldis2 & !secldis3);
_X033 = EXP(!CURSTA2 & secldis0 & !secldis1 & secldis2 & !secldis3);
_X034 = EXP(!CURSTA2 & !secldis0 & secldis1 & secldis2 & !secldis3);
_EQ052 = _X016 & _X031 & _X032 & _X033 & _X034;
_X016 = EXP( CURSTA0 & CURSTA1 & !CURSTA2);
_X031 = EXP( CURSTA1 & secldis0 & !secldis1 & secldis2 & !secldis3);
_X032 = EXP( CURSTA1 & !secldis0 & secldis1 & secldis2 & !secldis3);
_X033 = EXP(!CURSTA2 & secldis0 & !secldis1 & secldis2 & !secldis3);
_X034 = EXP(!CURSTA2 & !secldis0 & secldis1 & secldis2 & !secldis3);
-- Node name is '~4423~1'
-- Equation name is '~4423~1', location is LC042, type is buried.
-- synthesized logic cell
_LC042 = LCELL( _EQ053 $ VCC);
_EQ053 = !hourhdis0 & !hourhdis1 & !_LC024 & !_LC051 & !_LC059 & _X015 &
_X019
# !CURSTA0 & CURSTA1 & !CURSTA2 & !_LC051 & _X003 & _X019
# CURSTA0 & !CURSTA1 & !CURSTA2 & !hourhdis0 & !hourhdis1 & _X015
# !_LC024 & !_LC059 & _X002 & _X003;
_X015 = EXP(!hourhdis0 & !hourhdis1);
_X019 = EXP(!hourldis0 & !hourldis1 & !hourldis2 & !hourldis3);
_X003 = EXP( CURSTA0 & !CURSTA1 & !CURSTA2);
_X002 = EXP(!CURSTA0 & CURSTA1 & !CURSTA2);
-- Node name is '~4439~1'
-- Equation name is '~4439~1', location is LC060, type is buried.
-- synthesized logic cell
_LC060 = LCELL( _EQ054 $ GND);
_EQ054 = CURSTA0 & CURSTA1 & !CURSTA2 & minhdis0 & minhdis2
# CURSTA0 & CURSTA1 & !CURSTA2 & !minhdis0 & !minhdis2
# CURSTA0 & CURSTA1 & !CURSTA2 & minhdis1;
-- Node name is '~4440~1'
-- Equation name is '~4440~1', location is LC026, type is buried.
-- synthesized logic cell
_LC026 = LCELL( _EQ055 $ _EQ056);
_EQ055 = !CURSTA0 & !CURSTA1 & CURSTA2 & minldis0 & !minldis1 & !minldis2 &
!minldis3 & _X016 & _X021 & _X026 & _X027 & _X028
# !CURSTA0 & !CURSTA1 & CURSTA2 & !minldis0 & !minldis1 & minldis2 &
!minldis3 & _X016 & _X021 & _X026 & _X027 & _X028
# CURSTA0 & !CURSTA1 & CURSTA2 & sechdis0 & !sechdis1 & !sechdis2 &
_X016 & _X021 & _X026 & _X027 & _X028
# CURSTA0 & !CURSTA1 & CURSTA2 & !sechdis0 & !sechdis1 & sechdis2 &
_X016 & _X021 & _X026 & _X027 & _X028;
_X016 = EXP( CURSTA0 & CURSTA1 & !CURSTA2);
_X021 = EXP(!CURSTA2 & secldis0 & !secldis1 & !secldis2 & !secldis3);
_X026 = EXP( CURSTA1 & secldis0 & !secldis1 & !secldis2 & !secldis3);
_X027 = EXP( CURSTA1 & !secldis0 & !secldis1 & secldis2 & !secldis3);
_X028 = EXP(!CURSTA2 & !secldis0 & !secldis1 & secldis2 & !secldis3);
_EQ056 = _X016 & _X021 & _X026 & _X027 & _X028;
_X016 = EXP( CURSTA0 & CURSTA1 & !CURSTA2);
_X021 = EXP(!CURSTA2 & secldis0 & !secldis1 & !secldis2 & !secldis3);
_X026 = EXP( CURSTA1 & secldis0 & !secldis1 & !secldis2 & !secldis3);
_X027 = EXP( CURSTA1 & !secldis0 & !secldis1 & secldis2 & !secldis3);
_X028 = EXP(!CURSTA2 & !secldis0 & !secldis1 & secldis2 & !secldis3);
-- Node name is '~4444~1'
-- Equation name is '~4444~1', location is LC047, type is buried.
-- synthesized logic cell
_LC047 = LCELL( _EQ057 $ VCC);
_EQ057 = !hourhdis1 & !hourldis1 & !hourldis2 & !hourldis3 & !_LC026 &
!_LC060 & _X015 & _X019
# !hourhdis1 & !hourldis0 & !hourldis1 & !hourldis3 & !_LC026 &
!_LC060 & _X015 & _X019
# !CURSTA0 & CURSTA1 & !CURSTA2 & !_LC050 & _X003 & _X019
# CURSTA0 & !CURSTA1 & !CURSTA2 & !hourhdis1 & _X015
# !_LC026 & !_LC060 & _X002 & _X003;
_X015 = EXP(!hourhdis0 & !hourhdis1);
_X019 = EXP(!hourldis0 & !hourldis1 & !hourldis2 & !hourldis3);
_X003 = EXP( CURSTA0 & !CURSTA1 & !CURSTA2);
_X002 = EXP(!CURSTA0 & CURSTA1 & !CURSTA2);
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs A, C
-- _X002 occurs in LABs A, C, D
-- _X003 occurs in LABs C, D
-- _X015 occurs in LABs C, D
-- _X016 occurs in LABs A, B
-- _X019 occurs in LABs C, D
Project Information d:\clock5\clock5\clock2\display5.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,043K
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