📄 display5.rpt
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Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------- LC11 SECDIS1
| +----------------- LC8 SECDIS2
| | +--------------- LC5 SECDIS3
| | | +------------- LC4 SECDIS4
| | | | +----------- LC1 SECDIS5
| | | | | +--------- LC3 SECDIS6
| | | | | | +------- LC9 ~4330~1
| | | | | | | +----- LC6 ~4338~1
| | | | | | | | +--- LC12 ~4356~1
| | | | | | | | | +- LC2 ~4356~2
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | A B C D | Logic cells that feed LAB 'A':
LC9 -> - - - - - - - * - - | * - - - | <-- ~4330~1
LC2 -> - - - - - - - - * - | * - - - | <-- ~4356~2
Pin
1 -> - - - - - - - - - - | - - * * | <-- hourhdis1
20 -> - - - - - - * - - * | * * - * | <-- minldis0
36 -> - - - - - - * - * - | * * - * | <-- minldis1
33 -> - - - - - - * - * - | * * - * | <-- minldis2
21 -> - - - - - - * - * - | * * - * | <-- minldis3
2 -> - - - - - - - - - - | - - * - | <-- RESET
43 -> - - - - - - - - - - | - - - - | <-- SCLK
19 -> - - - - - - * - * - | * * - * | <-- sechdis0
27 -> - - - - - - * - * - | * * - * | <-- sechdis1
4 -> - - - - - - * - * - | * * - * | <-- sechdis2
5 -> - - - - - - * - * - | * * - * | <-- secldis0
32 -> - - - - - - * - - * | * * - * | <-- secldis1
44 -> - - - - - - * - - * | * * - * | <-- secldis2
34 -> - - - - - - * - - * | * * - * | <-- secldis3
17 -> - * - - - - - - - - | * * - - | <-- weekdis0
16 -> - * - - - - - - - - | * * - - | <-- weekdis1
39 -> - * - - - - - - - - | * * - - | <-- weekdis2
LC34 -> * * * * * * * * * * | * * * * | <-- CURSTA2
LC39 -> * * * * * * * * * * | * * * * | <-- CURSTA1
LC44 -> * * * * * * * * * * | * * * * | <-- CURSTA0
LC20 -> - - - - - * - - - - | * - - - | <-- ~1003~1
LC18 -> - - - - * - - - - - | * - - - | <-- ~1033~1
LC32 -> - - - * - - - - - - | * - - - | <-- ~1063~1
LC30 -> - - * - - - - - - - | * - - - | <-- ~1093~1
LC28 -> * - - - - - - - - - | * - - - | <-- ~1153~1
LC49 -> - - - - - - - * - - | * - - - | <-- ~2500~1
LC61 -> - - - - - * - - - - | * - - - | <-- ~4318~1
LC37 -> - - - - * - - - - - | * - - - | <-- ~4339~1
LC55 -> - - - * - - - - - - | * - - - | <-- ~4360~1
LC43 -> - - * - - - - - - - | * - - - | <-- ~4381~1
LC56 -> - * - - - - - - - - | * - - - | <-- ~4402~1
LC42 -> * - - - - - - - - - | * - - - | <-- ~4423~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\clock5\clock5\clock2\display5.rpt
display5
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------- LC20 ~1003~1
| +--------------- LC18 ~1033~1
| | +------------- LC32 ~1063~1
| | | +----------- LC30 ~1093~1
| | | | +--------- LC28 ~1153~1
| | | | | +------- LC19 ~1183~1
| | | | | | +----- LC27 ~4377~1
| | | | | | | +--- LC24 ~4419~1
| | | | | | | | +- LC26 ~4440~1
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
Pin
1 -> - - - - - - - - - | - - * * | <-- hourhdis1
20 -> - - - - - - * * * | * * - * | <-- minldis0
36 -> - - - - - - * * * | * * - * | <-- minldis1
33 -> - - - - - - * * * | * * - * | <-- minldis2
21 -> - - - - - - * * * | * * - * | <-- minldis3
2 -> - - - - - - - - - | - - * - | <-- RESET
43 -> - - - - - - - - - | - - - - | <-- SCLK
19 -> - - - - - - * * * | * * - * | <-- sechdis0
27 -> - - - - - - * * * | * * - * | <-- sechdis1
4 -> - - - - - - * * * | * * - * | <-- sechdis2
5 -> - - - - - - * * * | * * - * | <-- secldis0
32 -> - - - - - - * * * | * * - * | <-- secldis1
44 -> - - - - - - * * * | * * - * | <-- secldis2
34 -> - - - - - - * * * | * * - * | <-- secldis3
17 -> * * * * * * - - - | * * - - | <-- weekdis0
16 -> * * * * * * - - - | * * - - | <-- weekdis1
39 -> * * * * * * - - - | * * - - | <-- weekdis2
LC34 -> - - - - - - * * * | * * * * | <-- CURSTA2
LC39 -> - - - - - - * * * | * * * * | <-- CURSTA1
LC44 -> - - - - - - * * * | * * * * | <-- CURSTA0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\clock5\clock5\clock2\display5.rpt
display5
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------------------- LC36 ADDSEL0
| +------------------------- LC33 ADDSEL1
| | +----------------------- LC46 ADDSEL2
| | | +--------------------- LC40 SECDIS0
| | | | +------------------- LC41 SECDIS7
| | | | | +----------------- LC34 CURSTA2
| | | | | | +--------------- LC39 CURSTA1
| | | | | | | +------------- LC44 CURSTA0
| | | | | | | | +----------- LC35 ~4214~1
| | | | | | | | | +--------- LC38 ~4224~1
| | | | | | | | | | +------- LC37 ~4339~1
| | | | | | | | | | | +----- LC43 ~4381~1
| | | | | | | | | | | | +--- LC42 ~4423~1
| | | | | | | | | | | | | +- LC47 ~4444~1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC34 -> * * * * - * * * * * * * * * | * * * * | <-- CURSTA2
LC39 -> * * * * - * * * * * * * * * | * * * * | <-- CURSTA1
LC44 -> * * * * - * * * * * * * * * | * * * * | <-- CURSTA0
LC47 -> - - - * - - - - - - - - - - | - - * - | <-- ~4444~1
Pin
40 -> - - - - - - - - - - * * * * | - - * * | <-- hourhdis0
1 -> - - - - - - - - - - * * * * | - - * * | <-- hourhdis1
25 -> - - - - - - - - - - - * * * | - - * * | <-- hourldis0
13 -> - - - - - - - - - - - * * * | - - * * | <-- hourldis1
14 -> - - - - - - - - - - - * * * | - - * * | <-- hourldis2
18 -> - - - - - - - - - - - * * * | - - * * | <-- hourldis3
2 -> - - - - - * * * - - - - - - | - - * - | <-- RESET
43 -> - - - - - - - - - - - - - - | - - - - | <-- SCLK
44 -> - - - - - - - - - - - - - - | * * - * | <-- secldis2
LC19 -> - - - * - - - - - - - - - - | - - * - | <-- ~1183~1
LC52 -> - - - - - - - - - - - * - - | - - * - | <-- ~2073~1
LC51 -> - - - - - - - - - - - - * - | - - * - | <-- ~2133~1
LC50 -> - - - - - - - - - - - - - * | - - * - | <-- ~2163~1
LC53 -> - - - - - - - - - - * - - - | - - * - | <-- ~4337~1
LC6 -> - - - - - - - - - - * - - - | - - * - | <-- ~4338~1
LC64 -> - - - - - - - - - - - * - - | - - * - | <-- ~4376~1
LC27 -> - - - - - - - - - - - * - - | - - * - | <-- ~4377~1
LC59 -> - - - - - - - - - - - - * - | - - * - | <-- ~4418~1
LC24 -> - - - - - - - - - - - - * - | - - * - | <-- ~4419~1
LC60 -> - - - - - - - - - - - - - * | - - * - | <-- ~4439~1
LC26 -> - - - - - - - - - - - - - * | - - * - | <-- ~4440~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\clock5\clock5\clock2\display5.rpt
display5
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC63 ~2043~1
| +----------------------------- LC52 ~2073~1
| | +--------------------------- LC51 ~2133~1
| | | +------------------------- LC50 ~2163~1
| | | | +----------------------- LC49 ~2500~1
| | | | | +--------------------- LC61 ~4318~1
| | | | | | +------------------- LC54 ~4318~2
| | | | | | | +----------------- LC53 ~4337~1
| | | | | | | | +--------------- LC62 ~4355~1
| | | | | | | | | +------------- LC55 ~4360~1
| | | | | | | | | | +----------- LC64 ~4376~1
| | | | | | | | | | | +--------- LC56 ~4402~1
| | | | | | | | | | | | +------- LC57 ~4402~2
| | | | | | | | | | | | | +----- LC58 ~4402~3
| | | | | | | | | | | | | | +--- LC59 ~4418~1
| | | | | | | | | | | | | | | +- LC60 ~4439~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC63 -> - - - - - - - - - * - - - - - - | - - - * | <-- ~2043~1
LC54 -> - - - - - * - - - - - - - - - - | - - - * | <-- ~4318~2
LC62 -> - - - - - - - - - * - - - - - - | - - - * | <-- ~4355~1
LC57 -> - - - - - - - - - - - * - - - - | - - - * | <-- ~4402~2
LC58 -> - - - - - - - - - - - * - - - - | - - - * | <-- ~4402~3
Pin
40 -> - - - - - - - - - * - * - - - - | - - * * | <-- hourhdis0
1 -> - - - - - * - - - * - * - - - - | - - * * | <-- hourhdis1
25 -> * * * * - * - * - * - * - - - - | - - * * | <-- hourldis0
13 -> * * * * - * * * - * - * - - - - | - - * * | <-- hourldis1
14 -> * * * * - * * * - * - * - - - - | - - * * | <-- hourldis2
18 -> * * * * - * * * - * - * - - - - | - - * * | <-- hourldis3
41 -> - - - - * * - - * - * * - * * * | - - - * | <-- minhdis0
38 -> - - - - * * - - * - * * - * * * | - - - * | <-- minhdis1
37 -> - - - - * * - - * - * * - * * * | - - - * | <-- minhdis2
20 -> - - - - - * - - - - - * * - - - | * * - * | <-- minldis0
36 -> - - - - - * * - - - - * * - - - | * * - * | <-- minldis1
33 -> - - - - - * * - - - - * * - - - | * * - * | <-- minldis2
21 -> - - - - - * * - - - - * * - - - | * * - * | <-- minldis3
2 -> - - - - - - - - - - - - - - - - | - - * - | <-- RESET
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- SCLK
19 -> - - - - - - * - - - - * * - - - | * * - * | <-- sechdis0
27 -> - - - - - * * - - - - * * - - - | * * - * | <-- sechdis1
4 -> - - - - - * * - - - - * * - - - | * * - * | <-- sechdis2
5 -> - - - - - * * - - - - * - * - - | * * - * | <-- secldis0
32 -> - - - - - * * - - - - * - * - - | * * - * | <-- secldis1
44 -> - - - - - * * - - - - * - * - - | * * - * | <-- secldis2
34 -> - - - - - * * - - - - * - * - - | * * - * | <-- secldis3
LC34 -> - - - - - * * * * * * * * * * * | * * * * | <-- CURSTA2
LC39 -> - - - - - * * * * * * * * * * * | * * * * | <-- CURSTA1
LC44 -> - - - - - * * * * * * * * * * * | * * * * | <-- CURSTA0
LC35 -> - - - - - - - - - - - - * * - - | - - - * | <-- ~4214~1
LC38 -> - - - - - - - - - - - * * * - - | - - - * | <-- ~4224~1
LC12 -> - - - - - - - - - * - - - - - - | - - - * | <-- ~4356~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\clock5\clock5\clock2\display5.rpt
display5
** EQUATIONS **
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
RESET : INPUT;
SCLK : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
secldis0 : INPUT;
secldis1 : INPUT;
secldis2 : INPUT;
secldis3 : INPUT;
weekdis0 : INPUT;
weekdis1 : INPUT;
weekdis2 : INPUT;
-- Node name is 'ADDSEL0'
-- Equation name is 'ADDSEL0', location is LC036, type is output.
ADDSEL0 = LCELL( _EQ001 $ _EQ002);
_EQ001 = CURSTA0 & CURSTA1 & !CURSTA2 & _X001 & _X002
# CURSTA0 & !CURSTA1 & CURSTA2 & _X001 & _X002
# CURSTA0 & !CURSTA1 & !CURSTA2 & _X001;
_X001 = EXP(!CURSTA0 & !CURSTA1 & !CURSTA2);
_X002 = EXP(!CURSTA0 & CURSTA1 & !CURSTA2);
_EQ002 = _X001;
_X001 = EXP(!CURSTA0 & !CURSTA1 & !CURSTA2);
-- Node name is 'ADDSEL1'
-- Equation name is 'ADDSEL1', location is LC033, type is output.
ADDSEL1 = LCELL( _EQ003 $ _EQ004);
_EQ003 = CURSTA0 & CURSTA1 & !CURSTA2 & _X001 & _X002 & _X003
# !CURSTA0 & !CURSTA1 & CURSTA2 & _X001 & _X002 & _X003;
_X001 = EXP(!CURSTA0 & !CURSTA1 & !CURSTA2);
_X002 = EXP(!CURSTA0 & CURSTA1 & !CURSTA2);
_X003 = EXP( CURSTA0 & !CURSTA1 & !CURSTA2);
_EQ004 = _X001;
_X001 = EXP(!CURSTA0 & !CURSTA1 & !CURSTA2);
-- Node name is 'ADDSEL2'
-- Equation name is 'ADDSEL2', location is LC046, type is output.
ADDSEL2 = LCELL( _EQ005 $ GND);
_EQ005 = _X001 & _X002 & _X003;
_X001 = EXP(!CURSTA0 & !CURSTA1 & !CURSTA2);
_X002 = EXP(!CURSTA0 & CURSTA1 & !CURSTA2);
_X003 = EXP( CURSTA0 & !CURSTA1 & !CURSTA2);
-- Node name is ':42' = 'CURSTA0'
-- Equation name is 'CURSTA0', location is LC044, type is buried.
CURSTA0 = TFFE(!_EQ006, GLOBAL( SCLK), VCC, VCC, !RESET);
_EQ006 = !CURSTA0 & CURSTA1 & CURSTA2;
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