📄 display5.rpt
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Project Information d:\clock5\clock5\clock2\display5.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/27/2008 16:33:22
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
DISPLAY5
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
display5 EPM7064LC44-7 25 11 0 49 41 76 %
User Pins: 25 11 0
Project Information d:\clock5\clock5\clock2\display5.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'SECDIS7' is stuck at GND
Project Information d:\clock5\clock5\clock2\display5.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'SCLK' chosen for auto global Clock
Device-Specific Information: d:\clock5\clock5\clock2\display5.rpt
display5
***** Logic for device 'display5' compiled without errors.
Device: EPM7064LC44-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
Device-Specific Information: d:\clock5\clock5\clock2\display5.rpt
display5
** ERROR SUMMARY **
Info: Chip 'display5' in device 'EPM7064LC44-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
h h
s s o s m o
S e e u e i u
E c c r c n r
C l h R h l h h
D d d E d d S d d
I i i V S i i C G i i
S s s C E s s L N s s
1 0 2 C T 1 2 K D 0 0
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
SECDIS2 | 7 39 | weekdis2
SECDIS3 | 8 38 | minhdis1
SECDIS4 | 9 37 | minhdis2
GND | 10 36 | minldis1
SECDIS6 | 11 35 | VCC
SECDIS5 | 12 EPM7064LC44-7 34 | secldis3
hourldis1 | 13 33 | minldis2
hourldis2 | 14 32 | secldis1
VCC | 15 31 | ADDSEL2
weekdis1 | 16 30 | GND
weekdis0 | 17 29 | SECDIS7
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
h s m m G V A h A s S
o e i i N C D o D e E
u c n n D C D u D c C
r h l l S r S h D
l d d d E l E d I
d i i i L d L i S
i s s s 1 i 0 s 0
s 0 0 3 s 1
3 0
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\clock5\clock5\clock2\display5.rpt
display5
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 10/16( 62%) 8/ 8(100%) 15/16( 93%) 31/36( 86%)
B: LC17 - LC32 9/16( 56%) 8/ 8(100%) 16/16(100%) 17/36( 47%)
C: LC33 - LC48 14/16( 87%) 8/ 8(100%) 6/16( 37%) 23/36( 63%)
D: LC49 - LC64 16/16(100%) 8/ 8(100%) 16/16(100%) 31/36( 86%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 49/64 ( 76%)
Total shareable expanders used: 41/64 ( 64%)
Total Turbo logic cells used: 49/64 ( 76%)
Total shareable expanders not available (n/a): 12/64 ( 18%)
Average fan-in: 7.28
Total fan-in: 357
Total input pins required: 25
Total output pins required: 11
Total bidirectional pins required: 0
Total logic cells required: 49
Total flipflops required: 3
Total product terms required: 196
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 34
Synthesized logic cells: 35/ 64 ( 54%)
Device-Specific Information: d:\clock5\clock5\clock2\display5.rpt
display5
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
40 (62) (D) INPUT 0 0 0 0 0 0 6 hourhdis0
1 - - INPUT 0 0 0 0 0 0 7 hourhdis1
25 (35) (C) INPUT 0 0 0 0 0 0 11 hourldis0
13 (32) (B) INPUT 0 0 0 0 0 0 12 hourldis1
14 (30) (B) INPUT 0 0 0 0 0 0 12 hourldis2
18 (21) (B) INPUT 0 0 0 0 0 0 12 hourldis3
41 (64) (D) INPUT 0 0 0 0 0 0 8 minhdis0
38 (56) (D) INPUT 0 0 0 0 0 0 8 minhdis1
37 (53) (D) INPUT 0 0 0 0 0 0 8 minhdis2
20 (19) (B) INPUT 0 0 0 0 0 0 8 minldis0
36 (52) (D) INPUT 0 0 0 0 0 0 9 minldis1
33 (49) (D) INPUT 0 0 0 0 0 0 9 minldis2
21 (17) (B) INPUT 0 0 0 0 0 0 9 minldis3
2 - - INPUT 0 0 0 0 0 0 3 RESET
43 - - INPUT G 0 0 0 0 0 0 0 SCLK
19 (20) (B) INPUT 0 0 0 0 0 0 8 sechdis0
27 (37) (C) INPUT 0 0 0 0 0 0 9 sechdis1
4 (16) (A) INPUT 0 0 0 0 0 0 9 sechdis2
5 (14) (A) INPUT 0 0 0 0 0 0 9 secldis0
32 (48) (C) INPUT 0 0 0 0 0 0 9 secldis1
44 - - INPUT 0 0 0 0 0 0 9 secldis2
34 (51) (D) INPUT 0 0 0 0 0 0 9 secldis3
17 (24) (B) INPUT 0 0 0 0 0 1 6 weekdis0
16 (25) (B) INPUT 0 0 0 0 0 1 6 weekdis1
39 (57) (D) INPUT 0 0 0 0 0 1 6 weekdis2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\clock5\clock5\clock2\display5.rpt
display5
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
26 36 C OUTPUT t 2 2 0 0 3 0 0 ADDSEL0
24 33 C OUTPUT t 3 3 0 0 3 0 0 ADDSEL1
31 46 C OUTPUT t 3 3 0 0 3 0 0 ADDSEL2
28 40 C OUTPUT t 1 1 0 0 5 0 0 SECDIS0
6 11 A OUTPUT t 1 1 0 0 5 0 0 SECDIS1
7 8 A OUTPUT t 2 1 0 3 4 0 0 SECDIS2
8 5 A OUTPUT t 1 1 0 0 5 0 0 SECDIS3
9 4 A OUTPUT t 1 1 0 0 5 0 0 SECDIS4
12 1 A OUTPUT t 1 1 0 0 5 0 0 SECDIS5
11 3 A OUTPUT t 1 1 0 0 5 0 0 SECDIS6
29 41 C OUTPUT t 0 0 0 0 0 0 0 SECDIS7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\clock5\clock5\clock2\display5.rpt
display5
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 34 C DFFE + t 0 0 0 1 3 10 27 CURSTA2 (:40)
- 39 C TFFE + t 0 0 0 1 3 10 27 CURSTA1 (:41)
- 44 C TFFE + t 0 0 0 1 3 10 27 CURSTA0 (:42)
(19) 20 B SOFT s t 0 0 0 3 0 1 0 ~1003~1
- 18 B SOFT s t 0 0 0 3 0 1 0 ~1033~1
(13) 32 B SOFT s t 0 0 0 3 0 1 0 ~1063~1
(14) 30 B SOFT s t 0 0 0 3 0 1 0 ~1093~1
- 28 B SOFT s t 0 0 0 3 0 1 0 ~1153~1
(20) 19 B SOFT s t 0 0 0 3 0 1 0 ~1183~1
- 63 D SOFT s t 0 0 0 4 0 0 1 ~2043~1
(36) 52 D SOFT s t 0 0 0 4 0 0 1 ~2073~1
(34) 51 D SOFT s t 0 0 0 4 0 0 1 ~2133~1
- 50 D SOFT s t 0 0 0 4 0 0 1 ~2163~1
(33) 49 D SOFT s t 0 0 0 3 0 0 1 ~2500~1
(25) 35 C SOFT s t 0 0 0 0 3 0 2 ~4214~1
- 38 C SOFT s t 0 0 0 0 3 0 3 ~4224~1
- 61 D SOFT s t 5 0 1 18 4 1 0 ~4318~1
- 54 D SOFT s t 1 0 1 13 3 0 1 ~4318~2
- 9 A SOFT s t 7 0 1 11 3 0 1 ~4330~1
(37) 53 D SOFT s t 0 0 0 4 3 0 1 ~4337~1
- 6 A SOFT s t 1 1 0 0 5 0 1 ~4338~1
(27) 37 C SOFT s t 2 2 0 2 5 1 0 ~4339~1
(40) 62 D SOFT s t 0 0 0 3 3 0 1 ~4355~1
- 12 A SOFT s t 4 1 1 7 4 0 1 ~4356~1
- 2 A SOFT s t 1 0 1 4 3 0 1 ~4356~2
- 55 D SOFT s t 5 4 0 6 6 1 0 ~4360~1
(41) 64 D SOFT s t 0 0 0 3 3 0 1 ~4376~1
- 27 B SOFT s t 10 5 1 11 3 0 1 ~4377~1
- 43 C SOFT s t 4 4 0 6 6 1 0 ~4381~1
(38) 56 D SOFT s t 5 2 1 20 6 1 0 ~4402~1
(39) 57 D SOFT s t 1 0 1 7 5 0 1 ~4402~2
- 58 D SOFT s t 1 0 1 7 5 0 1 ~4402~3
- 59 D SOFT s t 0 0 0 3 3 0 1 ~4418~1
(17) 24 B SOFT s t 6 1 1 11 3 0 1 ~4419~1
- 42 C SOFT s t 4 4 0 6 6 1 0 ~4423~1
- 60 D SOFT s t 0 0 0 3 3 0 1 ~4439~1
- 26 B SOFT s t 6 5 1 11 3 0 1 ~4440~1
- 47 C SOFT s t 5 4 1 6 6 1 0 ~4444~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\clock5\clock5\clock2\display5.rpt
display5
** LOGIC CELL INTERCONNECTIONS **
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