📄 mux3.rpt
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Project Information c:\clock4\clock2\mux3.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/27/2008 13:12:38
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
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a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
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***** Project compilation was successful
MUX3
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
mux3 EPM7096QC100-7 47 23 0 23 0 23 %
User Pins: 47 23 0
Device-Specific Information: c:\clock4\clock2\mux3.rpt
mux3
***** Logic for device 'mux3' compiled without errors.
Device: EPM7096QC100-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: c:\clock4\clock2\mux3.rpt
mux3
** ERROR SUMMARY **
Info: Chip 'mux3' in device 'EPM7096QC100-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
h h h
o m o o m
u i u u i
V r n r r n
C h h V l l h
N C d d N C d d d
b b b G . b b I G G G G G i i . C i i i
1 1 1 N C 1 3 N N N N N N s s C I s s s
3 2 1 D . 0 2 T D D D D D 0 1 . O 2 3 0
------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 |_
/ 99 97 95 93 91 89 87 85 83 81 |
b20 | 1 80 | hourhdis1
b21 | 2 79 | hourldis0
b22 | 3 78 | hourldis1
b30 | 4 77 | minhdis2
VCCIO | 5 76 | GND
b31 | 6 75 | minldis0
a00 | 7 74 | minldis1
sel | 8 73 | minldis2
N.C. | 9 72 | N.C.
b51 | 10 71 | RESERVED
a22 | 11 70 | weekdis2
b52 | 12 69 | weekdis1
GND | 13 68 | VCCIO
b53 | 14 67 | weekdis0
a30 | 15 66 | secldis3
b60 | 16 EPM7096QC100-7 65 | secldis2
a31 | 17 64 | secldis1
b61 | 18 63 | secldis0
b62 | 19 62 | sechdis2
VCCIO | 20 61 | GND
b00 | 21 60 | minldis3
b40 | 22 59 | sechdis0
b33 | 23 58 | sechdis1
N.C. | 24 57 | N.C.
a10 | 25 56 | RESERVED
a52 | 26 55 | a60
b01 | 27 54 | a61
GND | 28 53 | VCCIO
a11 | 29 52 | a40
a53 | 30 51 | a62
| 32 34 36 38 40 42 44 46 48 50 _|
\ 31 33 35 37 39 41 43 45 47 49 |
\-------------------------------------------
b a a b a V N a b G V a a N G a a a a a
4 1 1 4 2 C . 2 5 N C 5 0 . N 5 4 3 4 3
1 2 3 2 0 C C 1 0 D C 1 1 C D 0 2 2 1 3
I . I .
O N
T
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: c:\clock4\clock2\mux3.rpt
mux3
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 0/16( 0%) 11/12( 91%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 11/16( 68%) 11/12( 91%) 0/16( 0%) 23/36( 63%)
F: LC81 - LC96 12/16( 75%) 12/12(100%) 0/16( 0%) 25/36( 69%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 70/72 ( 97%)
Total logic cells used: 23/96 ( 23%)
Total shareable expanders used: 0/96 ( 0%)
Total Turbo logic cells used: 23/96 ( 23%)
Total shareable expanders not available (n/a): 0/96 ( 0%)
Average fan-in: 3.00
Total fan-in: 69
Total input pins required: 47
Total output pins required: 23
Total bidirectional pins required: 0
Total logic cells required: 23
Total flipflops required: 0
Total product terms required: 46
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 96 ( 0%)
Device-Specific Information: c:\clock4\clock2\mux3.rpt
mux3
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
7 (3) (A) INPUT 0 0 0 0 0 1 0 a00
43 (51) (D) INPUT 0 0 0 0 0 1 0 a01
25 (48) (C) INPUT 0 0 0 0 0 1 0 a10
29 (44) (C) INPUT 0 0 0 0 0 1 0 a11
32 (40) (C) INPUT 0 0 0 0 0 1 0 a12
33 (38) (C) INPUT 0 0 0 0 0 1 0 a13
35 (36) (C) INPUT 0 0 0 0 0 1 0 a20
38 (35) (C) INPUT 0 0 0 0 0 1 0 a21
11 (30) (B) INPUT 0 0 0 0 0 1 0 a22
15 (27) (B) INPUT 0 0 0 0 0 1 0 a30
17 (24) (B) INPUT 0 0 0 0 0 1 0 a31
48 (54) (D) INPUT 0 0 0 0 0 1 0 a32
50 (57) (D) INPUT 0 0 0 0 0 1 0 a33
52 (60) (D) INPUT 0 0 0 0 0 1 0 a40
49 (56) (D) INPUT 0 0 0 0 0 1 0 a41
47 (53) (D) INPUT 0 0 0 0 0 1 0 a42
46 (52) (D) INPUT 0 0 0 0 0 1 0 a50
42 (49) (D) INPUT 0 0 0 0 0 1 0 a51
26 (46) (C) INPUT 0 0 0 0 0 1 0 a52
30 (43) (C) INPUT 0 0 0 0 0 1 0 a53
55 (62) (D) INPUT 0 0 0 0 0 1 0 a60
54 (61) (D) INPUT 0 0 0 0 0 1 0 a61
51 (59) (D) INPUT 0 0 0 0 0 1 0 a62
21 (20) (B) INPUT 0 0 0 0 0 1 0 b00
27 (45) (C) INPUT 0 0 0 0 0 1 0 b01
95 (14) (A) INPUT 0 0 0 0 0 1 0 b10
98 (13) (A) INPUT 0 0 0 0 0 1 0 b11
99 (12) (A) INPUT 0 0 0 0 0 1 0 b12
100 (11) (A) INPUT 0 0 0 0 0 1 0 b13
1 (9) (A) INPUT 0 0 0 0 0 1 0 b20
2 (8) (A) INPUT 0 0 0 0 0 1 0 b21
3 (6) (A) INPUT 0 0 0 0 0 1 0 b22
4 (5) (A) INPUT 0 0 0 0 0 1 0 b30
6 (4) (A) INPUT 0 0 0 0 0 1 0 b31
94 (16) (A) INPUT 0 0 0 0 0 1 0 b32
23 (17) (B) INPUT 0 0 0 0 0 1 0 b33
22 (19) (B) INPUT 0 0 0 0 0 1 0 b40
31 (41) (C) INPUT 0 0 0 0 0 1 0 b41
34 (37) (C) INPUT 0 0 0 0 0 1 0 b42
39 (33) (C) INPUT 0 0 0 0 0 1 0 b50
10 (32) (B) INPUT 0 0 0 0 0 1 0 b51
12 (29) (B) INPUT 0 0 0 0 0 1 0 b52
14 (28) (B) INPUT 0 0 0 0 0 1 0 b53
16 (25) (B) INPUT 0 0 0 0 0 1 0 b60
18 (22) (B) INPUT 0 0 0 0 0 1 0 b61
19 (21) (B) INPUT 0 0 0 0 0 1 0 b62
8 (1) (A) INPUT 0 0 0 0 0 23 0 sel
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\clock4\clock2\mux3.rpt
mux3
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
87 96 F OUTPUT t 0 0 0 3 0 0 0 hourhdis0
80 89 F OUTPUT t 0 0 0 3 0 0 0 hourhdis1
79 88 F OUTPUT t 0 0 0 3 0 0 0 hourldis0
78 86 F OUTPUT t 0 0 0 3 0 0 0 hourldis1
83 93 F OUTPUT t 0 0 0 3 0 0 0 hourldis2
82 92 F OUTPUT t 0 0 0 3 0 0 0 hourldis3
81 91 F OUTPUT t 0 0 0 3 0 0 0 minhdis0
86 94 F OUTPUT t 0 0 0 3 0 0 0 minhdis1
77 85 F OUTPUT t 0 0 0 3 0 0 0 minhdis2
75 84 F OUTPUT t 0 0 0 3 0 0 0 minldis0
74 83 F OUTPUT t 0 0 0 3 0 0 0 minldis1
73 81 F OUTPUT t 0 0 0 3 0 0 0 minldis2
60 68 E OUTPUT t 0 0 0 3 0 0 0 minldis3
59 67 E OUTPUT t 0 0 0 3 0 0 0 sechdis0
58 65 E OUTPUT t 0 0 0 3 0 0 0 sechdis1
62 69 E OUTPUT t 0 0 0 3 0 0 0 sechdis2
63 70 E OUTPUT t 0 0 0 3 0 0 0 secldis0
64 72 E OUTPUT t 0 0 0 3 0 0 0 secldis1
65 73 E OUTPUT t 0 0 0 3 0 0 0 secldis2
66 75 E OUTPUT t 0 0 0 3 0 0 0 secldis3
67 76 E OUTPUT t 0 0 0 3 0 0 0 weekdis0
69 77 E OUTPUT t 0 0 0 3 0 0 0 weekdis1
70 78 E OUTPUT t 0 0 0 3 0 0 0 weekdis2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\clock4\clock2\mux3.rpt
mux3
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+--------------------- LC68 minldis3
| +------------------- LC67 sechdis0
| | +----------------- LC65 sechdis1
| | | +--------------- LC69 sechdis2
| | | | +------------- LC70 secldis0
| | | | | +----------- LC72 secldis1
| | | | | | +--------- LC73 secldis2
| | | | | | | +------- LC75 secldis3
| | | | | | | | +----- LC76 weekdis0
| | | | | | | | | +--- LC77 weekdis1
| | | | | | | | | | +- LC78 weekdis2
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'E'
LC | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'E':
Pin
50 -> * - - - - - - - - - - | - - - - * - | <-- a33
52 -> - * - - - - - - - - - | - - - - * - | <-- a40
49 -> - - * - - - - - - - - | - - - - * - | <-- a41
47 -> - - - * - - - - - - - | - - - - * - | <-- a42
46 -> - - - - * - - - - - - | - - - - * - | <-- a50
42 -> - - - - - * - - - - - | - - - - * - | <-- a51
26 -> - - - - - - * - - - - | - - - - * - | <-- a52
30 -> - - - - - - - * - - - | - - - - * - | <-- a53
55 -> - - - - - - - - * - - | - - - - * - | <-- a60
54 -> - - - - - - - - - * - | - - - - * - | <-- a61
51 -> - - - - - - - - - - * | - - - - * - | <-- a62
23 -> * - - - - - - - - - - | - - - - * - | <-- b33
22 -> - * - - - - - - - - - | - - - - * - | <-- b40
31 -> - - * - - - - - - - - | - - - - * - | <-- b41
34 -> - - - * - - - - - - - | - - - - * - | <-- b42
39 -> - - - - * - - - - - - | - - - - * - | <-- b50
10 -> - - - - - * - - - - - | - - - - * - | <-- b51
12 -> - - - - - - * - - - - | - - - - * - | <-- b52
14 -> - - - - - - - * - - - | - - - - * - | <-- b53
16 -> - - - - - - - - * - - | - - - - * - | <-- b60
18 -> - - - - - - - - - * - | - - - - * - | <-- b61
19 -> - - - - - - - - - - * | - - - - * - | <-- b62
8 -> * * * * * * * * * * * | - - - - * * | <-- sel
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\clock4\clock2\mux3.rpt
mux3
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
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