📄 alarm3.rpt
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19 -> * - - - - - - - - - - - - - * - | - * | <-- hourhdis1
20 -> * - - - - - - - - - - - - * - - | - * | <-- hourldis0
21 -> * - - - - - - - - - - - * - - - | - * | <-- hourldis1
41 -> * - - - - - - - - - - * - - - - | - * | <-- hourldis2
40 -> * - - - - - - - - - * - - - - - | - * | <-- hourldis3
37 -> - - * - - - - - - * - - - - - - | - * | <-- minhdis0
36 -> - - * - - - - - * - - - - - - - | - * | <-- minhdis1
16 -> * - * - - - - * - - - - - - - - | - * | <-- minhdis2
14 -> * - - - - - * - - - - - - - - - | - * | <-- minldis0
5 -> * * - - - * - - - - - - - - - - | - * | <-- minldis1
6 -> - * - - * - - - - - - - - - - - | - * | <-- minldis2
8 -> - * - * - - - - - - - - - - - - | - * | <-- minldis3
31 -> * - - - - - - - - - - - - - - - | - * | <-- sechdis0
11 -> * - - - - - - - - - - - - - - - | - * | <-- sechdis1
12 -> * - - - - - - - - - - - - - - - | - * | <-- sechdis2
39 -> - - - * * * * * * * * * * * * * | * * | <-- settime
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\clock2\alarm3.rpt
alarm3
** EQUATIONS **
freq_l : INPUT;
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
settime : INPUT;
-- Node name is 'ALARM' = '~437~1'
-- Equation name is 'ALARM', location is LC001, type is output.
ALARM = LCELL( _EQ001 $ GND);
_EQ001 = freq_l & _LC024 & !settime
# ALARM & settime
# ALARM & freq_l & _LC024;
-- Node name is '~423~1'
-- Equation name is '~423~1', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ002 $ _EQ003);
_EQ002 = !_LC026 & !_LC027 & sechdis0 & sechdis1 & !sechdis2 & _X001 &
_X002 & _X003 & _X004 & _X005 & _X006 & _X007 & _X008 &
_X009 & _X010 & _X011 & _X012 & _X013
# !_LC026 & !_LC027 & !_LC032 & minldis0 & !sechdis2 & _X001 &
_X002 & _X003 & _X004 & _X005 & _X006 & _X007 & _X008 &
_X009 & _X010 & _X011 & _X012 & _X013
# !_LC026 & !_LC027 & _LC032 & !minldis0 & !sechdis2 & _X001 &
_X002 & _X003 & _X004 & _X005 & _X006 & _X007 & _X008 &
_X009 & _X010 & _X011 & _X012 & _X013
# !_LC026 & !_LC027 & !_LC030 & minldis1 & !sechdis2 & _X001 &
_X002 & _X003 & _X004 & _X005 & _X006 & _X007 & _X008 &
_X009 & _X010 & _X011 & _X012 & _X013;
_X001 = EXP(!hourldis2 & _LC022);
_X002 = EXP( _LC031 & !minhdis2);
_X003 = EXP(!hourhdis1 & _LC017);
_X004 = EXP( hourhdis1 & !_LC017);
_X005 = EXP(!hourhdis0 & _LC028);
_X006 = EXP( hourhdis0 & !_LC028);
_X007 = EXP(!hourldis3 & _LC023);
_X008 = EXP( hourldis3 & !_LC023);
_X009 = EXP( hourldis0 & !_LC019);
_X010 = EXP( hourldis2 & !_LC022);
_X011 = EXP(!hourldis1 & _LC021);
_X012 = EXP( hourldis1 & !_LC021);
_X013 = EXP(!hourldis0 & _LC019);
_EQ003 = !_LC026 & !_LC027 & !sechdis2 & _X001 & _X002 & _X003 & _X004 &
_X005 & _X006 & _X007 & _X008 & _X009 & _X010 & _X011 &
_X012 & _X013;
_X001 = EXP(!hourldis2 & _LC022);
_X002 = EXP( _LC031 & !minhdis2);
_X003 = EXP(!hourhdis1 & _LC017);
_X004 = EXP( hourhdis1 & !_LC017);
_X005 = EXP(!hourhdis0 & _LC028);
_X006 = EXP( hourhdis0 & !_LC028);
_X007 = EXP(!hourldis3 & _LC023);
_X008 = EXP( hourldis3 & !_LC023);
_X009 = EXP( hourldis0 & !_LC019);
_X010 = EXP( hourldis2 & !_LC022);
_X011 = EXP(!hourldis1 & _LC021);
_X012 = EXP( hourldis1 & !_LC021);
_X013 = EXP(!hourldis0 & _LC019);
-- Node name is '~423~2'
-- Equation name is '~423~2', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ004 $ GND);
_EQ004 = _LC030 & !minldis1
# !_LC018 & minldis2
# _LC018 & !minldis2
# !_LC020 & minldis3
# _LC020 & !minldis3;
-- Node name is '~423~3'
-- Equation name is '~423~3', location is LC026, type is buried.
-- synthesized logic cell
_LC026 = LCELL( _EQ005 $ GND);
_EQ005 = !_LC025 & minhdis0
# _LC025 & !minhdis0
# !_LC029 & minhdis1
# _LC029 & !minhdis1
# !_LC031 & minhdis2;
-- Node name is '~485~1'
-- Equation name is '~485~1', location is LC020, type is buried.
-- synthesized logic cell
_LC020 = LCELL( _EQ006 $ GND);
_EQ006 = minldis3 & settime
# _LC020 & !settime
# _LC020 & minldis3;
-- Node name is '~491~1'
-- Equation name is '~491~1', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ007 $ GND);
_EQ007 = minldis2 & settime
# _LC018 & !settime
# _LC018 & minldis2;
-- Node name is '~497~1'
-- Equation name is '~497~1', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ008 $ GND);
_EQ008 = minldis1 & settime
# _LC030 & !settime
# _LC030 & minldis1;
-- Node name is '~503~1'
-- Equation name is '~503~1', location is LC032, type is buried.
-- synthesized logic cell
_LC032 = LCELL( _EQ009 $ GND);
_EQ009 = minldis0 & settime
# _LC032 & !settime
# _LC032 & minldis0;
-- Node name is '~509~1'
-- Equation name is '~509~1', location is LC031, type is buried.
-- synthesized logic cell
_LC031 = LCELL( _EQ010 $ GND);
_EQ010 = minhdis2 & settime
# _LC031 & !settime
# _LC031 & minhdis2;
-- Node name is '~515~1'
-- Equation name is '~515~1', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ011 $ GND);
_EQ011 = minhdis1 & settime
# _LC029 & !settime
# _LC029 & minhdis1;
-- Node name is '~521~1'
-- Equation name is '~521~1', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ012 $ GND);
_EQ012 = minhdis0 & settime
# _LC025 & !settime
# _LC025 & minhdis0;
-- Node name is '~527~1'
-- Equation name is '~527~1', location is LC023, type is buried.
-- synthesized logic cell
_LC023 = LCELL( _EQ013 $ GND);
_EQ013 = hourldis3 & settime
# _LC023 & !settime
# hourldis3 & _LC023;
-- Node name is '~533~1'
-- Equation name is '~533~1', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ014 $ GND);
_EQ014 = hourldis2 & settime
# _LC022 & !settime
# hourldis2 & _LC022;
-- Node name is '~539~1'
-- Equation name is '~539~1', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ015 $ GND);
_EQ015 = hourldis1 & settime
# _LC021 & !settime
# hourldis1 & _LC021;
-- Node name is '~545~1'
-- Equation name is '~545~1', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ016 $ GND);
_EQ016 = hourldis0 & settime
# _LC019 & !settime
# hourldis0 & _LC019;
-- Node name is '~551~1'
-- Equation name is '~551~1', location is LC017, type is buried.
-- synthesized logic cell
_LC017 = LCELL( _EQ017 $ GND);
_EQ017 = hourhdis1 & settime
# _LC017 & !settime
# hourhdis1 & _LC017;
-- Node name is '~557~1'
-- Equation name is '~557~1', location is LC028, type is buried.
-- synthesized logic cell
_LC028 = LCELL( _EQ018 $ GND);
_EQ018 = hourhdis0 & settime
# _LC028 & !settime
# hourhdis0 & _LC028;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\clock2\alarm3.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,422K
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