📄 ring.vhd
字号:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ring IS
PORT(RESET: IN STD_LOGIC;
freq_h: IN STD_LOGIC;
freq_l: IN STD_LOGIC;
ALARM: OUT STD_LOGIC; --dirve signal for the bell
light: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
hourhdis: IN INTEGER RANGE 0 TO 2; --time information recieved from module of "clock"
hourldis: IN INTEGER RANGE 0 TO 9;
minhdis: IN INTEGER RANGE 0 TO 5;
minldis: IN INTEGER RANGE 0 TO 9;
sechdis: IN INTEGER RANGE 0 TO 5;
secldis: IN INTEGER RANGE 0 TO 9);
END ring;
ARCHITECTURE archi OF ring IS
BEGIN
PROCESS(secldis)
BEGIN --the clock alarm
IF reset='1' THEN
ALARM<='0';
ELSIF (minhdis=5 and minldis=9 and sechdis=5 and secldis=0) OR
(minhdis=5 and minldis=9 and sechdis=5 and secldis=2) OR
(minhdis=5 and minldis=9 and sechdis=5 and secldis=4) OR
(minhdis=5 and minldis=9 and sechdis=5 and secldis=6) OR
(minhdis=5 and minldis=9 and sechdis=5 and secldis=8) THEN
ALARM<=freq_l;
ELSIF (minhdis=0 and minldis=0 and sechdis=0 and secldis=0) THEN
ALARM<=freq_h;
ELSE ALARM<='0';
END IF;
IF reset='1' THEN --the industy control
light<="00000000";
ELSIF (hourhdis=0 and hourldis=8 and minhdis=3 and minldis=0) THEN
light<="00000001";
ELSIF (hourhdis=0 and hourldis=8 and minhdis=3 and minldis=1) THEN
light<="00000010";
ELSIF (hourhdis=0 and hourldis=8 and minhdis=3 and minldis=2) THEN
light<="00000010";
ELSIF (hourhdis=0 and hourldis=8 and minhdis=3 and minldis=3) THEN
light<="00000100";
ELSIF (hourhdis=0 and hourldis=8 and minhdis=3 and minldis=4) THEN
light<="00001000";
ELSIF (hourhdis=0 and hourldis=8 and minhdis=3 and minldis=5) THEN
light<="00001000";
ELSIF (hourhdis=0 and hourldis=8 and minhdis=3 and minldis=6) THEN
light<="01010000";
ELSIF (hourhdis=0 and hourldis=8 and minhdis=3 and minldis=7) THEN
light<="00000000";
ELSE light<="00000000";
END IF;
END PROCESS;
END archi;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -