freq_clock.vhd

数字钟的VHDL源程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY freq_clock IS
PORT(CLK: IN STD_LOGIC;
     clock_clk: OUT STD_LOGIC);
END ENTITY;

ARCHITECTURE freq_arc OF freq_clock IS
  SIGNAL cnt_1hz:STD_LOGIC;
BEGIN
PROCESS(CLK)
VARIABLE cnt:INTEGER RANGE 0 TO 512;
CONSTANT modu_1hz:INTEGER:=500;
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
  IF cnt=modu_1hz THEN
    cnt:=0;
    cnt_1hz<= NOT cnt_1hz;
    clock_clk<=cnt_1hz;
  END IF;
  cnt:=cnt+1;
END IF;
END PROCESS;
END freq_arc;