mux3.vhd

数字钟的VHDL源程序

library ieee;
use ieee.std_logic_1164.all;
entity mux3 is
port(
      a0:    IN INTEGER RANGE 0 TO 2;              
      a1:    IN INTEGER RANGE 0 TO 9;
      a2:    IN INTEGER RANGE 0 TO 5;
      a3:    IN INTEGER RANGE 0 TO 9;
      a4:    IN INTEGER RANGE 0 TO 5;
      a5:    IN INTEGER RANGE 0 TO 9;
      a6:    IN INTEGER RANGE 1 TO 7;
      b0:    IN INTEGER RANGE 0 TO 2;              
      b1:    IN INTEGER RANGE 0 TO 9;
      b2:    IN INTEGER RANGE 0 TO 5;
      b3:    IN INTEGER RANGE 0 TO 9;
      b4:    IN INTEGER RANGE 0 TO 5;
      b5:    IN INTEGER RANGE 0 TO 9;
      b6:    IN INTEGER RANGE 1 TO 7;
      hourhdis: OUT INTEGER RANGE 0 TO 2;
      hourldis: OUT INTEGER RANGE 0 TO 9;
      minhdis:  OUT INTEGER RANGE 0 TO 5;
      minldis:  OUT INTEGER RANGE 0 TO 9;
      sechdis:  OUT INTEGER RANGE 0 TO 5;
      secldis:  OUT INTEGER RANGE 0 TO 9;
      weekdis:  OUT INTEGER RANGE 1 TO 7;
      sel:in bit     );
end mux3;
architecture con of mux3 is
begin
process(a0,a1,a2,a3,a4,a5,a6,b0,b1,b2,b3,b4,b5,b6,sel)
begin
       if sel='0' then
          hourhdis<=a0;
          hourldis<=a1;
          minhdis<=a2;
          minldis<=a3;
          sechdis<=a4;
          secldis<=a5;
          weekdis<=a6;
       else
          hourhdis<=b0;
          hourldis<=b1;
          minhdis<=b2;
          minldis<=b3;
          sechdis<=b4;
          secldis<=b5;
          weekdis<=b6;
       end if;
end process;
end con;