freq_div.vhd

来自「数字钟的VHDL源程序」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY freq_div IS
  PORT(clk: IN STD_LOGIC;
       dou_clk,clock_clk,ringl_clk: OUT STD_LOGIC);
END ENTITY;

ARCHITECTURE freq_arc OF freq_div IS
  COMPONENT freq_clock IS
    PORT(clk:IN STD_LOGIC;
         clock_clk: OUT STD_LOGIC);
  END COMPONENT;
  COMPONENT freq_dou IS
    PORT(clk:IN STD_LOGIC;
         dou_clk: OUT STD_LOGIC);
  END COMPONENT;
  COMPONENT freq_ringl IS
    PORT(clk:IN STD_LOGIC;
         ringl_clk: OUT STD_LOGIC);
  END COMPONENT;
BEGIN
  U0:freq_clock PORT MAP(clk=>clk,clock_clk=>clock_clk);
  U1:freq_dou PORT MAP(clk=>clk,dou_clk=>dou_clk);
  U2:freq_ringl PORT MAP(clk=>clk,ringl_clk=>ringl_clk);
END freq_arc;