📄 alarm_clock.rpt
字号:
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: f:\clock2\alarm_clock.rpt
alarm_clock
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 1/2 1/2 10/22( 45%)
A2 8/ 8(100%) 2/ 8( 25%) 8/ 8(100%) 1/2 1/2 2/22( 9%)
A3 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
A4 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 2/2 8/22( 36%)
A6 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 6/22( 27%)
A7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
A9 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 2/2 1/2 5/22( 22%)
A11 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 1/2 8/22( 36%)
A13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A14 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 2/2 9/22( 40%)
A16 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 2/2 2/2 11/22( 50%)
A17 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
A19 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
A24 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 1/2 8/22( 36%)
A26 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 2/2 9/22( 40%)
A32 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 8/22( 36%)
A34 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 1/2 1/2 7/22( 31%)
A35 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 2/2 16/22( 72%)
C2 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 9/22( 40%)
C3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C4 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 2/2 9/22( 40%)
C5 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 10/22( 45%)
C6 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
C7 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 8/22( 36%)
C8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
C9 1/ 8( 12%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C10 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 2/2 11/22( 50%)
C11 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 2/2 14/22( 63%)
C13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C14 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 20/22( 90%)
C15 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 16/22( 72%)
C16 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
C17 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 1/2 9/22( 40%)
C18 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 19/22( 86%)
C19 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 5/22( 22%)
C20 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 5/22( 22%)
C22 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 20/22( 90%)
C23 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 20/22( 90%)
C24 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 8/22( 36%)
C25 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 20/22( 90%)
C26 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
C29 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
C31 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 7/22( 31%)
C33 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
C34 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 16/22( 72%)
E1 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
E11 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 2/2 9/22( 40%)
E13 7/ 8( 87%) 7/ 8( 87%) 6/ 8( 75%) 0/2 0/2 3/22( 13%)
E15 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
E18 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 9/22( 40%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 23/141 ( 16%)
Total logic cells used: 340/1728 ( 19%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.21/4 ( 80%)
Total fan-in: 1092/6912 ( 15%)
Total input pins required: 10
Total input I/O cell registers required: 0
Total output pins required: 13
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 340
Total flipflops required: 93
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 97/1728 ( 5%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 8 8 8 8 0 8 1 0 8 0 8 0 1 8 0 8 1 0 0 1 0 0 0 0 8 0 8 0 0 0 0 0 8 0 8 8 0 116/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 8 1 8 8 8 8 8 1 8 8 0 1 8 8 8 8 7 0 8 8 0 8 8 8 8 8 0 0 8 0 7 0 8 7 0 0 192/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 1 0 0 0 0 0 0 0 0 0 8 0 7 0 8 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 9 16 9 16 8 16 9 8 9 8 24 0 9 16 16 16 9 15 0 9 8 0 8 8 16 8 16 0 0 8 0 7 8 8 15 8 0 340/0
Device-Specific Information: f:\clock2\alarm_clock.rpt
alarm_clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
75 - - - 19 INPUT ^ 0 0 0 1 begend
189 - - - 21 INPUT ^ 0 0 0 26 begend2
83 - - - 17 INPUT ^ 0 0 0 2 clk_1hz
85 - - - 16 INPUT ^ 0 0 0 4 clk_1khz
86 - - - 15 INPUT ^ 0 0 0 5 clk_10hz
87 - - - 14 INPUT ^ 0 0 0 1 clk_500hz
88 - - - 14 INPUT ^ 0 0 0 1 enter
89 - - - 13 INPUT ^ 0 0 0 1 keyup
92 - - - 11 INPUT ^ 0 0 0 65 reset
93 - - - 10 INPUT ^ 0 0 0 1 sel
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\clock2\alarm_clock.rpt
alarm_clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
174 - - - 14 OUTPUT 0 1 0 0 addsel0
176 - - - 15 OUTPUT 0 1 0 0 addsel1
179 - - - 17 OUTPUT 0 1 0 0 addsel2
38 - - E -- OUTPUT 0 1 0 0 alarm
191 - - - 23 OUTPUT 0 1 0 0 alarm2
173 - - - 13 OUTPUT 0 1 0 0 secdis0
175 - - - 14 OUTPUT 0 1 0 0 secdis1
177 - - - 16 OUTPUT 0 1 0 0 secdis2
187 - - - 20 OUTPUT 0 1 0 0 secdis3
190 - - - 22 OUTPUT 0 1 0 0 secdis4
192 - - - 24 OUTPUT 0 1 0 0 secdis5
195 - - - 26 OUTPUT 0 1 0 0 secdis6
197 - - - 28 OUTPUT 0 0 0 0 secdis7
Code:
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