📄 alarm_clock.rpt
字号:
|control3:59|lpm_add_sub:246|addcore:adder|
|control3:59|lpm_add_sub:246|altshift:result_ext_latency_ffs|
|control3:59|lpm_add_sub:246|altshift:carry_ext_latency_ffs|
|control3:59|lpm_add_sub:246|altshift:oflow_ext_latency_ffs|
|control3:59|lpm_add_sub:270|
|control3:59|lpm_add_sub:270|addcore:adder|
|control3:59|lpm_add_sub:270|altshift:result_ext_latency_ffs|
|control3:59|lpm_add_sub:270|altshift:carry_ext_latency_ffs|
|control3:59|lpm_add_sub:270|altshift:oflow_ext_latency_ffs|
|control3:59|lpm_add_sub:296|
|control3:59|lpm_add_sub:296|addcore:adder|
|control3:59|lpm_add_sub:296|altshift:result_ext_latency_ffs|
|control3:59|lpm_add_sub:296|altshift:carry_ext_latency_ffs|
|control3:59|lpm_add_sub:296|altshift:oflow_ext_latency_ffs|
|control3:59|lpm_add_sub:323|
|control3:59|lpm_add_sub:323|addcore:adder|
|control3:59|lpm_add_sub:323|altshift:result_ext_latency_ffs|
|control3:59|lpm_add_sub:323|altshift:carry_ext_latency_ffs|
|control3:59|lpm_add_sub:323|altshift:oflow_ext_latency_ffs|
|control3:59|lpm_add_sub:349|
|control3:59|lpm_add_sub:349|addcore:adder|
|control3:59|lpm_add_sub:349|altshift:result_ext_latency_ffs|
|control3:59|lpm_add_sub:349|altshift:carry_ext_latency_ffs|
|control3:59|lpm_add_sub:349|altshift:oflow_ext_latency_ffs|
|control3:59|lpm_add_sub:376|
|control3:59|lpm_add_sub:376|addcore:adder|
|control3:59|lpm_add_sub:376|altshift:result_ext_latency_ffs|
|control3:59|lpm_add_sub:376|altshift:carry_ext_latency_ffs|
|control3:59|lpm_add_sub:376|altshift:oflow_ext_latency_ffs|
|control3:59|lpm_add_sub:402|
|control3:59|lpm_add_sub:402|addcore:adder|
|control3:59|lpm_add_sub:402|altshift:result_ext_latency_ffs|
|control3:59|lpm_add_sub:402|altshift:carry_ext_latency_ffs|
|control3:59|lpm_add_sub:402|altshift:oflow_ext_latency_ffs|
|clock5:56|
|clock5:56|lpm_add_sub:355|
|clock5:56|lpm_add_sub:355|addcore:adder|
|clock5:56|lpm_add_sub:355|altshift:result_ext_latency_ffs|
|clock5:56|lpm_add_sub:355|altshift:carry_ext_latency_ffs|
|clock5:56|lpm_add_sub:355|altshift:oflow_ext_latency_ffs|
|clock5:56|lpm_add_sub:402|
|clock5:56|lpm_add_sub:402|addcore:adder|
|clock5:56|lpm_add_sub:402|altshift:result_ext_latency_ffs|
|clock5:56|lpm_add_sub:402|altshift:carry_ext_latency_ffs|
|clock5:56|lpm_add_sub:402|altshift:oflow_ext_latency_ffs|
|clock5:56|lpm_add_sub:462|
|clock5:56|lpm_add_sub:462|addcore:adder|
|clock5:56|lpm_add_sub:462|altshift:result_ext_latency_ffs|
|clock5:56|lpm_add_sub:462|altshift:carry_ext_latency_ffs|
|clock5:56|lpm_add_sub:462|altshift:oflow_ext_latency_ffs|
|clock5:56|lpm_add_sub:590|
|clock5:56|lpm_add_sub:590|addcore:adder|
|clock5:56|lpm_add_sub:590|altshift:result_ext_latency_ffs|
|clock5:56|lpm_add_sub:590|altshift:carry_ext_latency_ffs|
|clock5:56|lpm_add_sub:590|altshift:oflow_ext_latency_ffs|
|clock5:56|lpm_add_sub:711|
|clock5:56|lpm_add_sub:711|addcore:adder|
|clock5:56|lpm_add_sub:711|altshift:result_ext_latency_ffs|
|clock5:56|lpm_add_sub:711|altshift:carry_ext_latency_ffs|
|clock5:56|lpm_add_sub:711|altshift:oflow_ext_latency_ffs|
|clock5:56|lpm_add_sub:858|
|clock5:56|lpm_add_sub:858|addcore:adder|
|clock5:56|lpm_add_sub:858|altshift:result_ext_latency_ffs|
|clock5:56|lpm_add_sub:858|altshift:carry_ext_latency_ffs|
|clock5:56|lpm_add_sub:858|altshift:oflow_ext_latency_ffs|
|clock5:56|lpm_add_sub:1028|
|clock5:56|lpm_add_sub:1028|addcore:adder|
|clock5:56|lpm_add_sub:1028|altshift:result_ext_latency_ffs|
|clock5:56|lpm_add_sub:1028|altshift:carry_ext_latency_ffs|
|clock5:56|lpm_add_sub:1028|altshift:oflow_ext_latency_ffs|
|display5:58|
|mux3:60|
|alarm4:61|
Device-Specific Information: f:\clock2\alarm_clock.rpt
alarm_clock
***** Logic for device 'alarm_clock' compiled without errors.
Device: EP1K30QC208-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E s E s E s s b s E E a s a s a s E E E E E E E E E E E E E E
S S S S S S S V S S S e S e S e a e e e S V S d e d e d e S S S S S S S S S S S S S S
E E E E E E E C E E E c E c V E c l c g c E C E d V c d c d c E E E E E E V E E E E E E E E
R R R R R R R C R R R d R d C R d a d e d R C R s C d s d s d R R R R R R C R R R R R R R R
V V V V V V V I V V V i V i C V i r i n G i V I G G G G V e C i e i e i V G V V V V V C V V V V V V V V
E E E E E E E N E E E s E s I E s m s d N s E N N N N N E l I s l s l s E N E E E E E I E E E E E E E E
D D D D D D D T D D D 7 D 6 O D 5 2 4 2 D 3 D T D D D D D 2 O 2 1 1 0 0 D D D D D D D O D D D D D D D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
RESERVED | 7 150 | RESERVED
RESERVED | 8 149 | RESERVED
RESERVED | 9 148 | RESERVED
RESERVED | 10 147 | RESERVED
RESERVED | 11 146 | VCCIO
RESERVED | 12 145 | GND
RESERVED | 13 144 | RESERVED
RESERVED | 14 143 | RESERVED
RESERVED | 15 142 | RESERVED
RESERVED | 16 141 | RESERVED
RESERVED | 17 140 | RESERVED
RESERVED | 18 139 | RESERVED
RESERVED | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | RESERVED
VCCIO | 22 135 | RESERVED
GND | 23 134 | RESERVED
RESERVED | 24 133 | RESERVED
RESERVED | 25 132 | RESERVED
RESERVED | 26 131 | RESERVED
RESERVED | 27 EP1K30QC208-3 130 | VCCINT
RESERVED | 28 129 | GND
RESERVED | 29 128 | RESERVED
RESERVED | 30 127 | RESERVED
RESERVED | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
RESERVED | 36 121 | RESERVED
RESERVED | 37 120 | RESERVED
alarm | 38 119 | RESERVED
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
RESERVED | 44 113 | RESERVED
RESERVED | 45 112 | RESERVED
RESERVED | 46 111 | RESERVED
RESERVED | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R R R R R V R R b G V G G G G G c V c c c e k R V r s R R R R V R R R R R R
E E E E E E N E E E E E E C E E E E E C E E e N C N N N N N l C l l l n e E C e e E E E E C E E E E E E
S S S S S S D S S S S S S C S S S S S C S S g D C D D D D D k C k k k t y S C s l S S S S C S S S S S S
E E E E E E E E E E E E I E E E E E I E E e I _ I _ _ _ e u E I e E E E E I E E E E E E
R R R R R R R R R R R R O R R R R R N R R n N 1 O 1 1 5 r p R N t R R R R O R R R R R R
V V V V V V V V V V V V V V V V V T V V d T h k 0 0 V T V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E z h h 0 E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D z z h D D D D D D D D D D D
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