df.vhd

数字钟的VHDL源程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY df IS
PORT(d,clk: IN STD_LOGIC;
     q,qn: OUT STD_LOGIC);
END df;

ARCHITECTURE df_arc OF df IS
BEGIN
  PROCESS(clk)
  BEGIN
  WAIT UNTIL clk'EVENT AND clk='1';
  q<=d;
  qn<= NOT d;
  END PROCESS;
END df_arc;