display2.rpt

数字钟的VHDL源程序

         # !secldis0 &  secldis1 &  secldis2 & !secldis3;

-- Node name is '~3757~2' 
-- Equation name is '~3757~2', location is LC7_C21, type is buried.
-- synthesized logic cell 
_LC7_C21 = LCELL( _EQ062);
  _EQ062 = !_LC5_C21 &  _LC6_C21
         #  _LC1_C21 & !_LC5_C21
         #  _LC5_C24;

-- Node name is '~3757~3' 
-- Equation name is '~3757~3', location is LC8_C21, type is buried.
-- synthesized logic cell 
_LC8_C21 = LCELL( _EQ063);
  _EQ063 = !sechdis0 &  sechdis1;

-- Node name is '~3757~4' 
-- Equation name is '~3757~4', location is LC4_C21, type is buried.
-- synthesized logic cell 
_LC4_C21 = LCELL( _EQ064);
  _EQ064 = !_LC7_C20 &  _LC7_C21
         #  _LC7_C20 &  _LC8_C21
         #  _LC2_C17 &  _LC7_C20;

-- Node name is '~3757~5' 
-- Equation name is '~3757~5', location is LC6_C13, type is buried.
-- synthesized logic cell 
_LC6_C13 = LCELL( _EQ065);
  _EQ065 = !minldis0 & !minldis1 & !minldis2 &  minldis3
         # !minldis0 &  minldis1 &  minldis2 & !minldis3;

-- Node name is '~3757~6' 
-- Equation name is '~3757~6', location is LC7_C13, type is buried.
-- synthesized logic cell 
_LC7_C13 = LCELL( _EQ066);
  _EQ066 =  _LC6_C13 & !_LC7_C22
         #  _LC1_C22 & !_LC7_C22
         #  _LC6_C22;

-- Node name is '~3757~7' 
-- Equation name is '~3757~7', location is LC3_C13, type is buried.
-- synthesized logic cell 
_LC3_C13 = LCELL( _EQ067);
  _EQ067 = !_LC4_C20 &  _LC4_C21 & !_LC8_C20
         # !_LC4_C20 &  _LC7_C13 &  _LC8_C20;

-- Node name is '~3757~8' 
-- Equation name is '~3757~8', location is LC6_C16, type is buried.
-- synthesized logic cell 
_LC6_C16 = LCELL( _EQ068);
  _EQ068 =  _LC4_C20 & !minhdis0 & !minhdis2
         #  _LC4_C20 & !minhdis0 &  minhdis1;

-- Node name is '~3757~9' 
-- Equation name is '~3757~9', location is LC5_C14, type is buried.
-- synthesized logic cell 
_LC5_C14 = LCELL( _EQ069);
  _EQ069 = !hourldis0 & !hourldis1 & !hourldis2 &  hourldis3
         # !hourldis0 &  hourldis1 &  hourldis2 & !hourldis3;

-- Node name is '~3757~10' 
-- Equation name is '~3757~10', location is LC1_C9, type is buried.
-- synthesized logic cell 
_LC1_C9  = LCELL( _EQ070);
  _EQ070 =  _LC5_C14 & !_LC8_C14
         #  _LC4_C14 & !_LC8_C14
         #  _LC6_C14;

-- Node name is '~3757~11' 
-- Equation name is '~3757~11', location is LC2_C9, type is buried.
-- synthesized logic cell 
_LC2_C9  = LCELL( _EQ071);
  _EQ071 =  _LC3_C13 & !_LC6_C20
         #  _LC6_C16 & !_LC6_C20
         #  _LC1_C9 &  _LC6_C20;

-- Node name is ':3757' 
-- Equation name is '_LC4_C9', type is buried 
_LC4_C9  = LCELL( _EQ072);
  _EQ072 =  _LC2_C9 & !_LC3_C20
         # !hourhdis0 &  _LC3_C20;

-- Node name is ':3763' 
-- Equation name is '_LC5_C13', type is buried 
_LC5_C13 = LCELL( _EQ073);
  _EQ073 =  _LC3_C21 & !_LC7_C20
         #  _LC5_C24 & !_LC7_C20
         #  _LC4_C17 &  _LC7_C20;

-- Node name is ':3770' 
-- Equation name is '_LC2_C18', type is buried 
_LC2_C18 = LCELL( _EQ074);
  _EQ074 =  _LC4_C20 & !minhdis0 &  minhdis1
         #  _LC4_C20 &  minhdis1 & !minhdis2
         #  _LC4_C20 & !minhdis0 & !minhdis2
         #  _LC4_C20 &  minhdis0 & !minhdis1 &  minhdis2;

-- Node name is ':3771' 
-- Equation name is '_LC4_C13', type is buried 
_LC4_C13 = LCELL( _EQ075);
  _EQ075 =  _LC2_C13 & !_LC4_C20 &  _LC8_C20
         # !_LC4_C20 &  _LC5_C13 & !_LC8_C20;

-- Node name is ':3772' 
-- Equation name is '_LC7_C18', type is buried 
_LC7_C18 = LCELL( _EQ076);
  _EQ076 =  _LC4_C13 & !_LC6_C20
         #  _LC2_C18 & !_LC6_C20
         #  _LC3_C18 &  _LC6_C20;

-- Node name is ':3775' 
-- Equation name is '_LC7_C19', type is buried 
_LC7_C19 = LCELL( _EQ077);
  _EQ077 = !_LC3_C20 &  _LC7_C18
         # !hourhdis0 &  _LC3_C20
         #  hourhdis1 &  _LC3_C20;

-- Node name is ':3781' 
-- Equation name is '_LC3_C19', type is buried 
_LC3_C19 = LCELL( _EQ078);
  _EQ078 = !_LC1_C21 & !_LC7_C20
         # !_LC1_C17 &  _LC7_C20;

-- Node name is ':3788' 
-- Equation name is '_LC5_C19', type is buried 
_LC5_C19 = LCELL( _EQ079);
  _EQ079 =  _LC4_C20 & !minhdis1
         #  _LC4_C20 &  minhdis0
         #  _LC4_C20 &  minhdis2;

-- Node name is ':3789' 
-- Equation name is '_LC4_C19', type is buried 
_LC4_C19 = LCELL( _EQ080);
  _EQ080 = !_LC1_C22 & !_LC4_C20 &  _LC8_C20
         #  _LC3_C19 & !_LC4_C20 & !_LC8_C20;

-- Node name is ':3790' 
-- Equation name is '_LC6_C19', type is buried 
_LC6_C19 = LCELL( _EQ081);
  _EQ081 =  _LC4_C19 & !_LC6_C20
         #  _LC5_C19 & !_LC6_C20
         # !_LC4_C14 &  _LC6_C20;

-- Node name is ':3793' 
-- Equation name is '_LC2_C19', type is buried 
_LC2_C19 = LCELL( _EQ082);
  _EQ082 = !_LC3_C20 &  _LC6_C19
         # !hourhdis1 &  _LC3_C20
         #  hourhdis0 &  _LC3_C20;

-- Node name is ':3799' 
-- Equation name is '_LC2_C15', type is buried 
_LC2_C15 = LCELL( _EQ083);
  _EQ083 = !_LC7_C20 &  _LC8_C24
         #  _LC6_C17 &  _LC7_C20
         #  _LC2_C17 &  _LC7_C20;

-- Node name is ':3806' 
-- Equation name is '_LC7_C16', type is buried 
_LC7_C16 = LCELL( _EQ084);
  _EQ084 =  _LC4_C20 & !minhdis2
         #  _LC4_C20 &  minhdis0 &  minhdis1
         #  _LC4_C20 & !minhdis0 & !minhdis1;

-- Node name is ':3807' 
-- Equation name is '_LC3_C15', type is buried 
_LC3_C15 = LCELL( _EQ085);
  _EQ085 =  _LC1_C15 & !_LC4_C20 &  _LC8_C20
         #  _LC2_C15 & !_LC4_C20 & !_LC8_C20;

-- Node name is ':3808' 
-- Equation name is '_LC8_C15', type is buried 
_LC8_C15 = LCELL( _EQ086);
  _EQ086 =  _LC3_C15 & !_LC6_C20
         # !_LC6_C20 &  _LC7_C16
         #  _LC6_C20 &  _LC7_C15;

-- Node name is ':3811' 
-- Equation name is '_LC5_C15', type is buried 
_LC5_C15 = LCELL( _EQ087);
  _EQ087 =  _LC8_C15
         #  _LC3_C20;

-- Node name is ':3817' 
-- Equation name is '_LC2_C24', type is buried 
_LC2_C24 = LCELL( _EQ088);
  _EQ088 =  _LC5_C24 & !_LC7_C20
         #  _LC1_C24 & !_LC7_C20
         #  _LC7_C17 &  _LC7_C20;

-- Node name is ':3820' 
-- Equation name is '_LC1_C13', type is buried 
_LC1_C13 = LCELL( _EQ089);
  _EQ089 =  _LC6_C22 &  _LC8_C20
         #  _LC4_C22 &  _LC8_C20
         #  _LC2_C24 & !_LC8_C20;

-- Node name is ':3823' 
-- Equation name is '_LC1_C23', type is buried 
_LC1_C23 = LCELL( _EQ090);
  _EQ090 =  _LC1_C13 & !_LC4_C20
         #  _LC2_C16 &  _LC4_C20
         #  _LC1_C18 &  _LC4_C20;

-- Node name is ':3826' 
-- Equation name is '_LC5_C23', type is buried 
_LC5_C23 = LCELL( _EQ091);
  _EQ091 =  _LC1_C23 & !_LC6_C20
         #  _LC6_C14 &  _LC6_C20
         #  _LC4_C15 &  _LC6_C20;

-- Node name is ':3829' 
-- Equation name is '_LC3_C23', type is buried 
_LC3_C23 = LCELL( _EQ092);
  _EQ092 = !_LC3_C20 &  _LC5_C23
         # !hourhdis0 &  _LC3_C20
         #  hourhdis1 &  _LC3_C20;

-- Node name is ':3849' 
-- Equation name is '_LC2_C23', type is buried 
_LC2_C23 = LCELL( _EQ093);
  _EQ093 = !_LC4_C20 &  _LC6_C23 &  _LC8_C20
         # !_LC4_C20 &  _LC6_C23 &  _LC7_C20;

-- Node name is ':3883' 
-- Equation name is '_LC4_C23', type is buried 
_LC4_C23 = LCELL( _EQ094);
  _EQ094 =  _LC3_C20
         # !_LC6_C20 &  _LC7_C20
         #  _LC4_C20 & !_LC6_C20;



Project Information                                     d:\clock2\display2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,116K