📄 display2.rpt
字号:
- 5 - C 24 AND2 4 0 0 6 :3366
- 6 - C 24 OR2 0 3 0 1 :3429
- 2 - C 21 OR2 4 0 0 1 :3482
- 3 - C 21 OR2 0 3 0 1 :3491
- 7 - C 24 OR2 4 0 0 1 :3539
- 4 - C 24 AND2 s 3 0 0 3 ~3549~1
- 8 - C 24 OR2 0 4 0 1 :3549
- 1 - C 24 OR2 4 0 0 2 :3581
- 7 - C 20 AND2 0 3 0 9 :3606
- 8 - C 20 AND2 0 3 0 9 :3616
- 4 - C 20 AND2 0 3 0 17 :3626
- 6 - C 20 OR2 ! 0 3 0 10 :3636
- 3 - C 20 AND2 0 3 0 10 :3646
- 6 - C 23 AND2 0 2 1 2 :3651
- 8 - C 23 OR2 0 3 1 0 :3667
- 1 - C 16 OR2 0 4 0 1 :3709
- 3 - C 17 OR2 s 3 0 0 1 ~3710~1
- 3 - C 24 OR2 s 4 0 0 2 ~3711~1
- 5 - C 22 OR2 s 4 0 0 1 ~3713~1
- 5 - C 16 OR2 3 1 0 1 :3716
- 4 - C 16 OR2 0 4 0 1 :3717
- 8 - C 16 OR2 0 4 0 1 :3718
- 1 - C 14 OR2 s 4 0 0 1 ~3719~1
- 3 - C 16 OR2 1 2 1 0 :3721
- 5 - C 17 OR2 0 4 0 1 :3727
- 8 - C 18 OR2 3 1 0 1 :3734
- 6 - C 18 OR2 0 4 0 1 :3735
- 4 - C 18 OR2 0 4 0 1 :3736
- 1 - C 19 OR2 2 2 1 0 :3739
- 6 - C 21 OR2 s 4 0 0 1 ~3757~1
- 7 - C 21 OR2 s 0 4 0 1 ~3757~2
- 8 - C 21 AND2 s 2 0 0 1 ~3757~3
- 4 - C 21 OR2 s 0 4 0 1 ~3757~4
- 6 - C 13 OR2 s 4 0 0 1 ~3757~5
- 7 - C 13 OR2 s 0 4 0 1 ~3757~6
- 3 - C 13 OR2 s 0 4 0 1 ~3757~7
- 6 - C 16 OR2 s 3 1 0 1 ~3757~8
- 5 - C 14 OR2 s 4 0 0 1 ~3757~9
- 1 - C 09 OR2 s 0 4 0 1 ~3757~10
- 2 - C 09 OR2 s 0 4 0 1 ~3757~11
- 4 - C 09 OR2 1 2 1 0 :3757
- 5 - C 13 OR2 0 4 0 1 :3763
- 2 - C 18 OR2 3 1 0 1 :3770
- 4 - C 13 OR2 0 4 0 1 :3771
- 7 - C 18 OR2 0 4 0 1 :3772
- 7 - C 19 OR2 2 2 1 0 :3775
- 3 - C 19 OR2 0 3 0 1 :3781
- 5 - C 19 OR2 3 1 0 1 :3788
- 4 - C 19 OR2 0 4 0 1 :3789
- 6 - C 19 OR2 0 4 0 1 :3790
- 2 - C 19 OR2 2 2 1 0 :3793
- 2 - C 15 OR2 0 4 0 1 :3799
- 7 - C 16 OR2 3 1 0 1 :3806
- 3 - C 15 OR2 0 4 0 1 :3807
- 8 - C 15 OR2 0 4 0 1 :3808
- 5 - C 15 OR2 0 2 1 0 :3811
- 2 - C 24 OR2 0 4 0 1 :3817
- 1 - C 13 OR2 0 4 0 1 :3820
- 1 - C 23 OR2 0 4 0 1 :3823
- 5 - C 23 OR2 0 4 0 1 :3826
- 3 - C 23 OR2 2 2 1 0 :3829
- 2 - C 23 OR2 0 4 0 1 :3849
- 4 - C 23 OR2 0 4 1 1 :3883
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\clock2\display2.rpt
display2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 40/ 96( 41%) 1/ 48( 2%) 36/ 48( 75%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\clock2\display2.rpt
display2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 SCLK
Device-Specific Information: d:\clock2\display2.rpt
display2
** EQUATIONS **
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
RESET : INPUT;
SCLK : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
secldis0 : INPUT;
secldis1 : INPUT;
secldis2 : INPUT;
secldis3 : INPUT;
-- Node name is 'ADDSEL0'
-- Equation name is 'ADDSEL0', type is output
ADDSEL0 = !_LC4_C23;
-- Node name is 'ADDSEL1'
-- Equation name is 'ADDSEL1', type is output
ADDSEL1 = _LC8_C23;
-- Node name is 'ADDSEL2'
-- Equation name is 'ADDSEL2', type is output
ADDSEL2 = _LC6_C23;
-- Node name is ':39' = 'CURSTA0'
-- Equation name is 'CURSTA0', location is LC1_C20, type is buried.
CURSTA0 = DFFE( _LC4_C23, GLOBAL( SCLK), VCC, VCC, !_LC1_C7);
-- Node name is ':38' = 'CURSTA1'
-- Equation name is 'CURSTA1', location is LC2_C20, type is buried.
CURSTA1 = DFFE( _EQ001, GLOBAL( SCLK), VCC, VCC, !_LC1_C7);
_EQ001 = !_LC3_C20 & _LC6_C20
# !_LC3_C20 & _LC4_C20;
-- Node name is ':37' = 'CURSTA2'
-- Equation name is 'CURSTA2', location is LC5_C20, type is buried.
CURSTA2 = DFFE( _LC2_C23, GLOBAL( SCLK), VCC, VCC, !_LC1_C7);
-- Node name is 'RESET~1'
-- Equation name is 'RESET~1', location is LC1_C7, type is buried.
-- synthesized logic cell
!_LC1_C7 = _LC1_C7~NOT;
_LC1_C7~NOT = LCELL(!RESET);
-- Node name is 'SECDIS0'
-- Equation name is 'SECDIS0', type is output
SECDIS0 = _LC3_C23;
-- Node name is 'SECDIS1'
-- Equation name is 'SECDIS1', type is output
SECDIS1 = _LC5_C15;
-- Node name is 'SECDIS2'
-- Equation name is 'SECDIS2', type is output
SECDIS2 = _LC2_C19;
-- Node name is 'SECDIS3'
-- Equation name is 'SECDIS3', type is output
SECDIS3 = _LC7_C19;
-- Node name is 'SECDIS4'
-- Equation name is 'SECDIS4', type is output
SECDIS4 = _LC4_C9;
-- Node name is 'SECDIS5'
-- Equation name is 'SECDIS5', type is output
SECDIS5 = _LC1_C19;
-- Node name is 'SECDIS6'
-- Equation name is 'SECDIS6', type is output
SECDIS6 = _LC3_C16;
-- Node name is 'SECDIS7'
-- Equation name is 'SECDIS7', type is output
SECDIS7 = GND;
-- Node name is ':1346'
-- Equation name is '_LC4_C14', type is buried
!_LC4_C14 = _LC4_C14~NOT;
_LC4_C14~NOT = LCELL( _EQ002);
_EQ002 = hourldis3
# hourldis0
# !hourldis1
# hourldis2;
-- Node name is ':1358'
-- Equation name is '_LC8_C14', type is buried
!_LC8_C14 = _LC8_C14~NOT;
_LC8_C14~NOT = LCELL( _EQ003);
_EQ003 = hourldis3
# !hourldis0
# hourldis1
# hourldis2;
-- Node name is ':1370'
-- Equation name is '_LC6_C14', type is buried
_LC6_C14 = LCELL( _EQ004);
_EQ004 = !hourldis0 & !hourldis1 & !hourldis2 & !hourldis3;
-- Node name is ':1433'
-- Equation name is '_LC7_C14', type is buried
_LC7_C14 = LCELL( _EQ005);
_EQ005 = hourldis3
# !hourldis1 & hourldis2
# !hourldis0 & !hourldis1
# !hourldis0 & hourldis2;
-- Node name is ':1486'
-- Equation name is '_LC2_C14', type is buried
_LC2_C14 = LCELL( _EQ006);
_EQ006 = hourldis3
# !hourldis2
# hourldis0 & !hourldis1
# !hourldis0 & hourldis1;
-- Node name is ':1493'
-- Equation name is '_LC3_C18', type is buried
_LC3_C18 = LCELL( _EQ007);
_EQ007 = _LC2_C14 & !_LC8_C14
# _LC3_C14 & !_LC8_C14
# _LC6_C14;
-- Node name is ':1543'
-- Equation name is '_LC6_C15', type is buried
_LC6_C15 = LCELL( _EQ008);
_EQ008 = hourldis3
# !hourldis2
# !hourldis0 & !hourldis1
# hourldis0 & hourldis1;
-- Node name is '~1553~1'
-- Equation name is '~1553~1', location is LC3_C14, type is buried.
-- synthesized logic cell
_LC3_C14 = LCELL( _EQ009);
_EQ009 = hourldis1 & !hourldis2 & !hourldis3;
-- Node name is ':1553'
-- Equation name is '_LC7_C15', type is buried
_LC7_C15 = LCELL( _EQ010);
_EQ010 = _LC3_C14
# _LC6_C15
# !_LC4_C15
# _LC6_C14;
-- Node name is ':1585'
-- Equation name is '_LC4_C15', type is buried
_LC4_C15 = LCELL( _EQ011);
_EQ011 = hourldis3
# hourldis1
# hourldis0 & hourldis2
# !hourldis0 & !hourldis2;
-- Node name is ':1859'
-- Equation name is '_LC2_C16', type is buried
_LC2_C16 = LCELL( _EQ012);
_EQ012 = !minhdis0 & !minhdis1 & !minhdis2;
-- Node name is ':2074'
-- Equation name is '_LC1_C18', type is buried
_LC1_C18 = LCELL( _EQ013);
_EQ013 = minhdis1
# !minhdis0 & !minhdis2
# minhdis0 & minhdis2;
-- Node name is ':2344'
-- Equation name is '_LC1_C22', type is buried
!_LC1_C22 = _LC1_C22~NOT;
_LC1_C22~NOT = LCELL( _EQ014);
_EQ014 = minldis3
# minldis0
# !minldis1
# minldis2;
-- Node name is ':2356'
-- Equation name is '_LC7_C22', type is buried
!_LC7_C22 = _LC7_C22~NOT;
_LC7_C22~NOT = LCELL( _EQ015);
_EQ015 = minldis3
# !minldis0
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