📄 display2.rpt
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Project Information d:\clock2\display2.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/26/2008 11:01:42
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
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net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
DISPLAY2
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
display2 EP1K10TC100-1 22 11 0 0 0 % 97 16 %
User Pins: 22 11 0
Device-Specific Information: d:\clock2\display2.rpt
display2
***** Logic for device 'display2' compiled without errors.
Device: EP1K10TC100-1
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Enable Lock Output = OFF
h h
s o R o m m m m R R R R R R R R R
e A u E u i i i i E E E E E E E E E
c D r S r n V n n n S S S S S S S S S ^
h D l E l h C l h l R E E E V E E E E E E D
# d S d R d d C d d d E R R R C R R R R R R A
T i E i V G i i I i i i G S V V V C V V V V V V T
C s L s E N s s N s s s N E E E E I E E E E E E A
K 0 2 1 D D 3 0 T 0 1 2 D T D D D O D D D D D D 0
----------------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 80 78 76 |_
/ 99 97 95 93 91 89 87 85 83 81 79 77 |
^CONF_DONE | 1 75 | ^DCLK
^nCEO | 2 74 | ^nCE
#TDO | 3 73 | #TDI
VCCIO | 4 72 | VCCINT
RESERVED | 5 71 | RESERVED
SECDIS2 | 6 70 | RESERVED
RESERVED | 7 69 | RESERVED
RESERVED | 8 68 | RESERVED
RESERVED | 9 67 | VCCIO
RESERVED | 10 66 | GND
GND | 11 65 | RESERVED
VCCINT | 12 64 | RESERVED
SECDIS5 | 13 EP1K10TC100-1 63 | RESERVED
SECDIS7 | 14 62 | RESERVED
RESERVED | 15 61 | RESERVED
RESERVED | 16 60 | VCCINT
VCCIO | 17 59 | GND
GND | 18 58 | sechdis2
sechdis1 | 19 57 | SECDIS0
minhdis2 | 20 56 | secldis3
ADDSEL0 | 21 55 | hourhdis0
SECDIS1 | 22 54 | ^MSEL0
SECDIS3 | 23 53 | ^MSEL1
#TMS | 24 52 | VCCINT
^nSTATUS | 25 51 | ^nCONFIG
| 27 29 31 33 35 37 39 41 43 45 47 49 _|
\ 26 28 30 32 34 36 38 40 42 44 46 48 50 |
\-----------------------------------------------------
A s h h h s S s R V G V m S m G G R V R R S R R R
D e o o o e E e E C N C i C i N N E C E E E E E E
D c u u u c C c S C D C n L n D D S C S S C S S S
S l r r r l D l E I _ l K l _ E I E E D E E E
E d l l h d I d R N C d d C R O R R I R R R
L i d d d i S i V T K i i K V V V S V V V
1 s i i i s 6 s E L s s L E E E 4 E E E
0 s s s 2 1 D K 3 1 K D D D D D D
0 2 1
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: d:\clock2\display2.rpt
display2
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
C7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C9 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
C13 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 18/22( 81%)
C14 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
C15 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 19/22( 86%)
C16 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
C17 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 5/22( 22%)
C18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 17/22( 77%)
C19 7/ 8( 87%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 16/22( 72%)
C20 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 3/22( 13%)
C21 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
C22 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
C23 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
C24 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 27/60 ( 45%)
Total logic cells used: 97/576 ( 16%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.64/4 ( 91%)
Total fan-in: 354/2304 ( 15%)
Total input pins required: 22
Total input I/O cell registers required: 0
Total output pins required: 11
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 97
Total flipflops required: 3
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 20/ 576 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 1 0 3 0 0 0 0 7 8 8 8 8 8 7 8 8 8 7 8 97/0
Total: 0 0 0 0 0 0 1 0 3 0 0 0 0 7 8 8 8 8 8 7 8 8 8 7 8 97/0
Device-Specific Information: d:\clock2\display2.rpt
display2
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - C -- INPUT ^ 0 0 0 5 hourhdis0
30 - - - 18 INPUT ^ 0 0 0 5 hourhdis1
28 - - - 20 INPUT ^ 0 0 0 9 hourldis0
97 - - - 23 INPUT ^ 0 0 0 10 hourldis1
29 - - - 19 INPUT ^ 0 0 0 10 hourldis2
94 - - - 19 INPUT ^ 0 0 0 10 hourldis3
93 - - - 13 INPUT ^ 0 0 0 8 minhdis0
90 - - - -- INPUT ^ 0 0 0 8 minhdis1
20 - - C -- INPUT ^ 0 0 0 8 minhdis2
91 - - - -- INPUT ^ 0 0 0 9 minldis0
40 - - - -- INPUT ^ 0 0 0 10 minldis1
89 - - - -- INPUT ^ 0 0 0 10 minldis2
38 - - - -- INPUT ^ 0 0 0 10 minldis3
87 - - - 12 INPUT ^ 0 0 0 1 RESET
39 - - - -- INPUT G ^ 0 0 0 0 SCLK
99 - - - 24 INPUT ^ 0 0 0 8 sechdis0
19 - - C -- INPUT ^ 0 0 0 8 sechdis1
58 - - C -- INPUT ^ 0 0 0 7 sechdis2
27 - - - 21 INPUT ^ 0 0 0 8 secldis0
33 - - - 15 INPUT ^ 0 0 0 9 secldis1
31 - - - 17 INPUT ^ 0 0 0 9 secldis2
56 - - C -- INPUT ^ 0 0 0 9 secldis3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\clock2\display2.rpt
display2
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - C -- OUTPUT 0 1 0 0 ADDSEL0
26 - - - 23 OUTPUT 0 1 0 0 ADDSEL1
98 - - - 24 OUTPUT 0 1 0 0 ADDSEL2
57 - - C -- OUTPUT 0 1 0 0 SECDIS0
22 - - C -- OUTPUT 0 1 0 0 SECDIS1
6 - - A -- OUTPUT 0 1 0 0 SECDIS2
23 - - C -- OUTPUT 0 1 0 0 SECDIS3
47 - - - 09 OUTPUT 0 1 0 0 SECDIS4
13 - - B -- OUTPUT 0 1 0 0 SECDIS5
32 - - - 16 OUTPUT 0 1 0 0 SECDIS6
14 - - B -- OUTPUT 0 0 0 0 SECDIS7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\clock2\display2.rpt
display2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 07 SOFT s ! 1 0 0 3 RESET~1
- 5 - C 20 DFFE + 0 2 0 5 CURSTA2 (:37)
- 2 - C 20 DFFE + 0 4 0 5 CURSTA1 (:38)
- 1 - C 20 DFFE + 0 2 0 5 CURSTA0 (:39)
- 4 - C 14 OR2 ! 4 0 0 2 :1346
- 8 - C 14 OR2 ! 4 0 0 2 :1358
- 6 - C 14 AND2 4 0 0 4 :1370
- 7 - C 14 OR2 4 0 0 1 :1433
- 2 - C 14 OR2 4 0 0 1 :1486
- 3 - C 18 OR2 0 4 0 1 :1493
- 6 - C 15 OR2 4 0 0 1 :1543
- 3 - C 14 AND2 s 3 0 0 2 ~1553~1
- 7 - C 15 OR2 0 4 0 1 :1553
- 4 - C 15 OR2 4 0 0 2 :1585
- 2 - C 16 AND2 3 0 0 1 :1859
- 1 - C 18 OR2 3 0 0 1 :2074
- 1 - C 22 OR2 ! 4 0 0 2 :2344
- 7 - C 22 OR2 ! 4 0 0 2 :2356
- 6 - C 22 AND2 4 0 0 4 :2368
- 5 - C 18 OR2 4 0 0 1 :2431
- 8 - C 22 OR2 4 0 0 1 :2484
- 2 - C 13 OR2 0 4 0 1 :2491
- 2 - C 22 OR2 4 0 0 1 :2541
- 3 - C 22 AND2 s 3 0 0 2 ~2551~1
- 1 - C 15 OR2 0 4 0 1 :2551
- 4 - C 22 OR2 4 0 0 2 :2583
- 1 - C 17 OR2 ! 3 0 0 1 :2837
- 2 - C 17 AND2 3 0 0 5 :2857
- 8 - C 17 OR2 3 0 0 1 :2922
- 4 - C 17 OR2 3 1 0 1 :2980
- 6 - C 17 OR2 s 3 0 0 1 ~3040~1
- 7 - C 17 OR2 3 1 0 1 :3070
- 1 - C 21 OR2 ! 4 0 0 2 :3342
- 5 - C 21 OR2 ! 4 0 0 2 :3354
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