alarm2.rpt

数字钟的VHDL源程序

A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
C:      11/ 96( 11%)     4/ 48(  8%)     3/ 48(  6%)    8/16( 50%)      1/16(  6%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                              d:\clock2\alarm2.rpt
alarm2

** EQUATIONS **

freq_l   : INPUT;
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
settime  : INPUT;

-- Node name is 'ALARM' 
-- Equation name is 'ALARM', type is output 
ALARM    =  _LC2_C19;

-- Node name is '~438~1' 
-- Equation name is '~438~1', location is LC1_C19, type is buried.
-- synthesized logic cell 
_LC1_C19 = LCELL( _EQ001);
  _EQ001 =  _LC3_C19 &  _LC4_C19 &  minhdis0 &  minhdis1
         #  _LC3_C19 & !_LC4_C19 &  minhdis0 & !minhdis1
         # !_LC3_C19 &  _LC4_C19 & !minhdis0 &  minhdis1
         # !_LC3_C19 & !_LC4_C19 & !minhdis0 & !minhdis1;

-- Node name is '~438~2' 
-- Equation name is '~438~2', location is LC7_C4, type is buried.
-- synthesized logic cell 
_LC7_C4  = LCELL( _EQ002);
  _EQ002 =  _LC3_C4 &  minldis3 & !sechdis0
         # !_LC3_C4 & !minldis3 & !sechdis0
         #  _LC3_C4 &  minldis3 & !sechdis1
         # !_LC3_C4 & !minldis3 & !sechdis1;

-- Node name is '~438~3' 
-- Equation name is '~438~3', location is LC7_C3, type is buried.
-- synthesized logic cell 
_LC7_C3  = LCELL( _EQ003);
  _EQ003 =  hourldis2 &  hourldis3 &  _LC3_C3 &  _LC4_C3
         #  hourldis2 & !hourldis3 &  _LC3_C3 & !_LC4_C3
         # !hourldis2 &  hourldis3 & !_LC3_C3 &  _LC4_C3
         # !hourldis2 & !hourldis3 & !_LC3_C3 & !_LC4_C3;

-- Node name is '~438~4' 
-- Equation name is '~438~4', location is LC8_C3, type is buried.
-- synthesized logic cell 
_LC8_C3  = LCELL( _EQ004);
  _EQ004 =  hourldis1 &  _LC5_C3 &  _LC6_C3 &  minldis2
         # !hourldis1 &  _LC5_C3 & !_LC6_C3 &  minldis2
         #  hourldis1 & !_LC5_C3 &  _LC6_C3 & !minldis2
         # !hourldis1 & !_LC5_C3 & !_LC6_C3 & !minldis2;

-- Node name is '~438~5' 
-- Equation name is '~438~5', location is LC1_C4, type is buried.
-- synthesized logic cell 
_LC1_C4  = LCELL( _EQ005);
  _EQ005 =  _LC2_C3 &  _LC2_C4 &  minldis0 &  minldis1
         # !_LC2_C3 &  _LC2_C4 &  minldis0 & !minldis1
         #  _LC2_C3 & !_LC2_C4 & !minldis0 &  minldis1
         # !_LC2_C3 & !_LC2_C4 & !minldis0 & !minldis1;

-- Node name is '~438~6' 
-- Equation name is '~438~6', location is LC1_C3, type is buried.
-- synthesized logic cell 
_LC1_C3  = LCELL( _EQ006);
  _EQ006 =  _LC1_C4 &  _LC7_C3 &  _LC8_C3;

-- Node name is '~438~7' 
-- Equation name is '~438~7', location is LC8_C4, type is buried.
-- synthesized logic cell 
_LC8_C4  = LCELL( _EQ007);
  _EQ007 =  hourldis0 &  _LC5_C4 &  _LC6_C4 &  minhdis2
         # !hourldis0 &  _LC5_C4 & !_LC6_C4 &  minhdis2
         #  hourldis0 & !_LC5_C4 &  _LC6_C4 & !minhdis2
         # !hourldis0 & !_LC5_C4 & !_LC6_C4 & !minhdis2;

-- Node name is '~438~8' 
-- Equation name is '~438~8', location is LC4_C4, type is buried.
-- synthesized logic cell 
_LC4_C4  = LCELL( _EQ008);
  _EQ008 =  _LC1_C3 &  _LC1_C19 &  _LC7_C4 &  _LC8_C4;

-- Node name is '~438~9' 
-- Equation name is '~438~9', location is LC7_C19, type is buried.
-- synthesized logic cell 
_LC7_C19 = LCELL( _EQ009);
  _EQ009 =  hourhdis0 &  hourhdis1 &  _LC5_C19 &  _LC6_C19
         #  hourhdis0 & !hourhdis1 &  _LC5_C19 & !_LC6_C19
         # !hourhdis0 &  hourhdis1 & !_LC5_C19 &  _LC6_C19
         # !hourhdis0 & !hourhdis1 & !_LC5_C19 & !_LC6_C19;

-- Node name is '~438~10' 
-- Equation name is '~438~10', location is LC8_C19, type is buried.
-- synthesized logic cell 
_LC8_C19 = LCELL( _EQ010);
  _EQ010 =  freq_l &  _LC7_C19 & !sechdis2 & !settime;

-- Node name is ':438' 
-- Equation name is '_LC2_C19', type is buried 
_LC2_C19 = LCELL( _EQ011);
  _EQ011 =  _LC2_C19 &  settime
         #  _LC4_C4 &  _LC8_C19;

-- Node name is ':486' 
-- Equation name is '_LC3_C4', type is buried 
_LC3_C4  = LCELL( _EQ012);
  _EQ012 =  _LC3_C4 & !settime
         #  minldis3 &  settime;

-- Node name is ':492' 
-- Equation name is '_LC5_C3', type is buried 
_LC5_C3  = LCELL( _EQ013);
  _EQ013 =  _LC5_C3 & !settime
         #  minldis2 &  settime;

-- Node name is ':498' 
-- Equation name is '_LC2_C3', type is buried 
_LC2_C3  = LCELL( _EQ014);
  _EQ014 =  _LC2_C3 & !settime
         #  minldis1 &  settime;

-- Node name is ':504' 
-- Equation name is '_LC2_C4', type is buried 
_LC2_C4  = LCELL( _EQ015);
  _EQ015 =  _LC2_C4 & !settime
         #  minldis0 &  settime;

-- Node name is ':510' 
-- Equation name is '_LC5_C4', type is buried 
_LC5_C4  = LCELL( _EQ016);
  _EQ016 =  _LC5_C4 & !settime
         #  minhdis2 &  settime;

-- Node name is ':516' 
-- Equation name is '_LC4_C19', type is buried 
_LC4_C19 = LCELL( _EQ017);
  _EQ017 =  _LC4_C19 & !settime
         #  minhdis1 &  settime;

-- Node name is ':522' 
-- Equation name is '_LC3_C19', type is buried 
_LC3_C19 = LCELL( _EQ018);
  _EQ018 =  _LC3_C19 & !settime
         #  minhdis0 &  settime;

-- Node name is ':528' 
-- Equation name is '_LC4_C3', type is buried 
_LC4_C3  = LCELL( _EQ019);
  _EQ019 =  _LC4_C3 & !settime
         #  hourldis3 &  settime;

-- Node name is ':534' 
-- Equation name is '_LC3_C3', type is buried 
_LC3_C3  = LCELL( _EQ020);
  _EQ020 =  _LC3_C3 & !settime
         #  hourldis2 &  settime;

-- Node name is ':540' 
-- Equation name is '_LC6_C3', type is buried 
_LC6_C3  = LCELL( _EQ021);
  _EQ021 =  _LC6_C3 & !settime
         #  hourldis1 &  settime;

-- Node name is ':546' 
-- Equation name is '_LC6_C4', type is buried 
_LC6_C4  = LCELL( _EQ022);
  _EQ022 =  _LC6_C4 & !settime
         #  hourldis0 &  settime;

-- Node name is ':552' 
-- Equation name is '_LC6_C19', type is buried 
_LC6_C19 = LCELL( _EQ023);
  _EQ023 =  _LC6_C19 & !settime
         #  hourhdis1 &  settime;

-- Node name is ':558' 
-- Equation name is '_LC5_C19', type is buried 
_LC5_C19 = LCELL( _EQ024);
  _EQ024 =  _LC5_C19 & !settime
         #  hourhdis0 &  settime;



Project Information                                       d:\clock2\alarm2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,973K