reg7b.vhd

来自「使用DDS技术」· VHDL 代码 · 共 16 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG7B IS
    PORT (  Load :  IN STD_LOGIC;
             DIN :  IN STD_LOGIC_VECTOR(6 DOWNTO 0);
            DOUT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );
END REG7B;
ARCHITECTURE behav OF REG7B IS
BEGIN
    PROCESS(Load, DIN)
   BEGIN
   IF Load'EVENT AND Load = '1' THEN    -- 时钟到来时，锁存输入数据
            DOUT <= DIN;
        END IF;
    END PROCESS;
END behav;