dds.tan.qmsg

使用DDS技术

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK dc_out fsk_decode:u7\|s 16.321 ns register " "Info: tco from clock \"CLK\" to destination pin \"dc_out\" through register \"fsk_decode:u7\|s\" is 16.321 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.730 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 7.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 50; CLK Node = 'CLK'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/DDS.VHD" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns fsk_decode:u7\|q\[7\] 2 REG LC_X8_Y13_N7 9 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N7; Fanout = 9; REG Node = 'fsk_decode:u7\|q\[7\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.966 ns" { CLK fsk_decode:u7|q[7] } "NODE_NAME" } } { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.584 ns) + CELL(0.711 ns) 7.730 ns fsk_decode:u7\|s 3 REG LC_X8_Y12_N4 1 " "Info: 3: + IC(3.584 ns) + CELL(0.711 ns) = 7.730 ns; Loc. = LC_X8_Y12_N4; Fanout = 1; REG Node = 'fsk_decode:u7\|s'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.295 ns" { fsk_decode:u7|q[7] fsk_decode:u7|s } "NODE_NAME" } } { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.30 % ) " "Info: Total cell delay = 3.115 ns ( 40.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.615 ns ( 59.70 % ) " "Info: Total interconnect delay = 4.615 ns ( 59.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.730 ns" { CLK fsk_decode:u7|q[7] fsk_decode:u7|s } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.730 ns" { CLK CLK~out0 fsk_decode:u7|q[7] fsk_decode:u7|s } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.367 ns + Longest register pin " "Info: + Longest register to pin delay is 8.367 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fsk_decode:u7\|s 1 REG LC_X8_Y12_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y12_N4; Fanout = 1; REG Node = 'fsk_decode:u7\|s'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fsk_decode:u7|s } "NODE_NAME" } } { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.243 ns) + CELL(2.124 ns) 8.367 ns dc_out 2 PIN PIN_167 0 " "Info: 2: + IC(6.243 ns) + CELL(2.124 ns) = 8.367 ns; Loc. = PIN_167; Fanout = 0; PIN Node = 'dc_out'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.367 ns" { fsk_decode:u7|s dc_out } "NODE_NAME" } } { "DDS.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/DDS.VHD" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 25.39 % ) " "Info: Total cell delay = 2.124 ns ( 25.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.243 ns ( 74.61 % ) " "Info: Total interconnect delay = 6.243 ns ( 74.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.367 ns" { fsk_decode:u7|s dc_out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.367 ns" { fsk_decode:u7|s dc_out } { 0.000ns 6.243ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.730 ns" { CLK fsk_decode:u7|q[7] fsk_decode:u7|s } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.730 ns" { CLK CLK~out0 fsk_decode:u7|q[7] fsk_decode:u7|s } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.367 ns" { fsk_decode:u7|s dc_out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.367 ns" { fsk_decode:u7|s dc_out } { 0.000ns 6.243ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 25 10:39:08 2007 " "Info: Processing ended: Mon Jun 25 10:39:08 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}