dds.tan.qmsg

使用DDS技术

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fsk_decode:u7\|q\[7\] " "Info: Detected ripple clock \"fsk_decode:u7\|q\[7\]\" as buffer" {  } { { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 16 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fsk_decode:u7\|q\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register ps7:u6\|q register REG7B:u2\|DOUT\[4\] 72.13 MHz 13.864 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 72.13 MHz between source register \"ps7:u6\|q\" and destination register \"REG7B:u2\|DOUT\[4\]\" (period= 13.864 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.113 ns + Longest register register " "Info: + Longest register to register delay is 2.113 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ps7:u6\|q 1 REG LC_X36_Y5_N0 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y5_N0; Fanout = 6; REG Node = 'ps7:u6\|q'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ps7:u6|q } "NODE_NAME" } } { "ps7.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/ps7.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.517 ns) + CELL(0.423 ns) 0.940 ns REG7B:u2\|DOUT\[0\]~28 2 COMB LC_X36_Y5_N1 2 " "Info: 2: + IC(0.517 ns) + CELL(0.423 ns) = 0.940 ns; Loc. = LC_X36_Y5_N1; Fanout = 2; COMB Node = 'REG7B:u2\|DOUT\[0\]~28'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.940 ns" { ps7:u6|q REG7B:u2|DOUT[0]~28 } "NODE_NAME" } } { "reg7b.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/reg7b.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.018 ns REG7B:u2\|DOUT\[1\]~29 3 COMB LC_X36_Y5_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.018 ns; Loc. = LC_X36_Y5_N2; Fanout = 2; COMB Node = 'REG7B:u2\|DOUT\[1\]~29'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { REG7B:u2|DOUT[0]~28 REG7B:u2|DOUT[1]~29 } "NODE_NAME" } } { "reg7b.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/reg7b.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.096 ns REG7B:u2\|DOUT\[2\]~30 4 COMB LC_X36_Y5_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.096 ns; Loc. = LC_X36_Y5_N3; Fanout = 2; COMB Node = 'REG7B:u2\|DOUT\[2\]~30'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { REG7B:u2|DOUT[1]~29 REG7B:u2|DOUT[2]~30 } "NODE_NAME" } } { "reg7b.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/reg7b.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.274 ns REG7B:u2\|DOUT\[3\]~31 5 COMB LC_X36_Y5_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.274 ns; Loc. = LC_X36_Y5_N4; Fanout = 3; COMB Node = 'REG7B:u2\|DOUT\[3\]~31'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { REG7B:u2|DOUT[2]~30 REG7B:u2|DOUT[3]~31 } "NODE_NAME" } } { "reg7b.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/reg7b.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.113 ns REG7B:u2\|DOUT\[4\] 6 REG LC_X36_Y5_N5 4 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.113 ns; Loc. = LC_X36_Y5_N5; Fanout = 4; REG Node = 'REG7B:u2\|DOUT\[4\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { REG7B:u2|DOUT[3]~31 REG7B:u2|DOUT[4] } "NODE_NAME" } } { "reg7b.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/reg7b.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.596 ns ( 75.53 % ) " "Info: Total cell delay = 1.596 ns ( 75.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.517 ns ( 24.47 % ) " "Info: Total interconnect delay = 0.517 ns ( 24.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.113 ns" { ps7:u6|q REG7B:u2|DOUT[0]~28 REG7B:u2|DOUT[1]~29 REG7B:u2|DOUT[2]~30 REG7B:u2|DOUT[3]~31 REG7B:u2|DOUT[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.113 ns" { ps7:u6|q REG7B:u2|DOUT[0]~28 REG7B:u2|DOUT[1]~29 REG7B:u2|DOUT[2]~30 REG7B:u2|DOUT[3]~31 REG7B:u2|DOUT[4] } { 0.000ns 0.517ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.178ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.558 ns - Smallest " "Info: - Smallest clock skew is -4.558 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.111 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 50; CLK Node = 'CLK'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/DDS.VHD" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns REG7B:u2\|DOUT\[4\] 2 REG LC_X36_Y5_N5 4 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X36_Y5_N5; Fanout = 4; REG Node = 'REG7B:u2\|DOUT\[4\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.642 ns" { CLK REG7B:u2|DOUT[4] } "NODE_NAME" } } { "reg7b.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/reg7b.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { CLK REG7B:u2|DOUT[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { CLK CLK~out0 REG7B:u2|DOUT[4] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.669 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 7.669 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 50; CLK Node = 'CLK'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/DDS.VHD" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns fsk_decode:u7\|q\[7\] 2 REG LC_X8_Y13_N7 9 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N7; Fanout = 9; REG Node = 'fsk_decode:u7\|q\[7\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.966 ns" { CLK fsk_decode:u7|q[7] } "NODE_NAME" } } { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.523 ns) + CELL(0.711 ns) 7.669 ns ps7:u6\|q 3 REG LC_X36_Y5_N0 6 " "Info: 3: + IC(3.523 ns) + CELL(0.711 ns) = 7.669 ns; Loc. = LC_X36_Y5_N0; Fanout = 6; REG Node = 'ps7:u6\|q'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.234 ns" { fsk_decode:u7|q[7] ps7:u6|q } "NODE_NAME" } } { "ps7.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/ps7.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.62 % ) " "Info: Total cell delay = 3.115 ns ( 40.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.554 ns ( 59.38 % ) " "Info: Total interconnect delay = 4.554 ns ( 59.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.669 ns" { CLK fsk_decode:u7|q[7] ps7:u6|q } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.669 ns" { CLK CLK~out0 fsk_decode:u7|q[7] ps7:u6|q } { 0.000ns 0.000ns 1.031ns 3.523ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { CLK REG7B:u2|DOUT[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { CLK CLK~out0 REG7B:u2|DOUT[4] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.669 ns" { CLK fsk_decode:u7|q[7] ps7:u6|q } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.669 ns" { CLK CLK~out0 fsk_decode:u7|q[7] ps7:u6|q } { 0.000ns 0.000ns 1.031ns 3.523ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ps7.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/ps7.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "reg7b.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/reg7b.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "ps7.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/ps7.vhd" 7 -1 0 } } { "reg7b.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/reg7b.vhd" 12 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.113 ns" { ps7:u6|q REG7B:u2|DOUT[0]~28 REG7B:u2|DOUT[1]~29 REG7B:u2|DOUT[2]~30 REG7B:u2|DOUT[3]~31 REG7B:u2|DOUT[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.113 ns" { ps7:u6|q REG7B:u2|DOUT[0]~28 REG7B:u2|DOUT[1]~29 REG7B:u2|DOUT[2]~30 REG7B:u2|DOUT[3]~31 REG7B:u2|DOUT[4] } { 0.000ns 0.517ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.111 ns" { CLK REG7B:u2|DOUT[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.111 ns" { CLK CLK~out0 REG7B:u2|DOUT[4] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.669 ns" { CLK fsk_decode:u7|q[7] ps7:u6|q } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.669 ns" { CLK CLK~out0 fsk_decode:u7|q[7] ps7:u6|q } { 0.000ns 0.000ns 1.031ns 3.523ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 5 " "Warning: Circuit may not operate. Detected 5 non-operational path(s) clocked by clock \"CLK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "fsk_decode:u7\|m\[4\] fsk_decode:u7\|s CLK 3.311 ns " "Info: Found hold time violation between source  pin or register \"fsk_decode:u7\|m\[4\]\" and destination pin or register \"fsk_decode:u7\|s\" for clock \"CLK\" (Hold time is 3.311 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.560 ns + Largest " "Info: + Largest clock skew is 4.560 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.730 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 7.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 50; CLK Node = 'CLK'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/DDS.VHD" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns fsk_decode:u7\|q\[7\] 2 REG LC_X8_Y13_N7 9 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N7; Fanout = 9; REG Node = 'fsk_decode:u7\|q\[7\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.966 ns" { CLK fsk_decode:u7|q[7] } "NODE_NAME" } } { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.584 ns) + CELL(0.711 ns) 7.730 ns fsk_decode:u7\|s 3 REG LC_X8_Y12_N4 1 " "Info: 3: + IC(3.584 ns) + CELL(0.711 ns) = 7.730 ns; Loc. = LC_X8_Y12_N4; Fanout = 1; REG Node = 'fsk_decode:u7\|s'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.295 ns" { fsk_decode:u7|q[7] fsk_decode:u7|s } "NODE_NAME" } } { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.30 % ) " "Info: Total cell delay = 3.115 ns ( 40.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.615 ns ( 59.70 % ) " "Info: Total interconnect delay = 4.615 ns ( 59.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.730 ns" { CLK fsk_decode:u7|q[7] fsk_decode:u7|s } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.730 ns" { CLK CLK~out0 fsk_decode:u7|q[7] fsk_decode:u7|s } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.170 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 50; CLK Node = 'CLK'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/DDS.VHD" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns fsk_decode:u7\|m\[4\] 2 REG LC_X8_Y12_N9 2 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X8_Y12_N9; Fanout = 2; REG Node = 'fsk_decode:u7\|m\[4\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { CLK fsk_decode:u7|m[4] } "NODE_NAME" } } { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { CLK fsk_decode:u7|m[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { CLK CLK~out0 fsk_decode:u7|m[4] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.730 ns" { CLK fsk_decode:u7|q[7] fsk_decode:u7|s } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.730 ns" { CLK CLK~out0 fsk_decode:u7|q[7] fsk_decode:u7|s } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { CLK fsk_decode:u7|m[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { CLK CLK~out0 fsk_decode:u7|m[4] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.040 ns - Shortest register register " "Info: - Shortest register to register delay is 1.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fsk_decode:u7\|m\[4\] 1 REG LC_X8_Y12_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y12_N9; Fanout = 2; REG Node = 'fsk_decode:u7\|m\[4\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fsk_decode:u7|m[4] } "NODE_NAME" } } { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.478 ns) 1.040 ns fsk_decode:u7\|s 2 REG LC_X8_Y12_N4 1 " "Info: 2: + IC(0.562 ns) + CELL(0.478 ns) = 1.040 ns; Loc. = LC_X8_Y12_N4; Fanout = 1; REG Node = 'fsk_decode:u7\|s'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.040 ns" { fsk_decode:u7|m[4] fsk_decode:u7|s } "NODE_NAME" } } { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 45.96 % ) " "Info: Total cell delay = 0.478 ns ( 45.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.562 ns ( 54.04 % ) " "Info: Total interconnect delay = 0.562 ns ( 54.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.040 ns" { fsk_decode:u7|m[4] fsk_decode:u7|s } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "1.040 ns" { fsk_decode:u7|m[4] fsk_decode:u7|s } { 0.000ns 0.562ns } { 0.000ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 30 -1 0 } } { "fsk_decode.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/fsk_mc/fsk_decode.vhd" 7 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.730 ns" { CLK fsk_decode:u7|q[7] fsk_decode:u7|s } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.730 ns" { CLK CLK~out0 fsk_decode:u7|q[7] fsk_decode:u7|s } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { CLK fsk_decode:u7|m[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { CLK CLK~out0 fsk_decode:u7|m[4] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.040 ns" { fsk_decode:u7|m[4] fsk_decode:u7|s } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "1.040 ns" { fsk_decode:u7|m[4] fsk_decode:u7|s } { 0.000ns 0.562ns } { 0.000ns 0.478ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}