dds.map.eqn

使用DDS技术

F1_m[4]_lut_out = F1_m[4] $ (!F1_m[4]_carry_eqn);
F1_m[4] = DFFEAS(F1_m[4]_lut_out, CLK, VCC, , , , , F1L3, );


--C1_DOUT[0] is REG7B:u2|DOUT[0]
--operation mode is arithmetic

C1_DOUT[0]_lut_out = E1_q $ !C1_DOUT[0];
C1_DOUT[0] = DFFEAS(C1_DOUT[0]_lut_out, CLK, VCC, , , , , , );

--C1L3 is REG7B:u2|DOUT[0]~50
--operation mode is arithmetic

C1L3 = CARRY(!E1_q & C1_DOUT[0]);


--C1_DOUT[1] is REG7B:u2|DOUT[1]
--operation mode is arithmetic

C1_DOUT[1]_carry_eqn = C1L3;
C1_DOUT[1]_lut_out = C1_DOUT[1] $ (C1_DOUT[1]_carry_eqn);
C1_DOUT[1] = DFFEAS(C1_DOUT[1]_lut_out, CLK, VCC, , , , , , );

--C1L5 is REG7B:u2|DOUT[1]~54
--operation mode is arithmetic

C1L5 = CARRY(!C1L3 # !C1_DOUT[1]);


--C1_DOUT[2] is REG7B:u2|DOUT[2]
--operation mode is arithmetic

C1_DOUT[2]_carry_eqn = C1L5;
C1_DOUT[2]_lut_out = E1_q $ C1_DOUT[2] $ !C1_DOUT[2]_carry_eqn;
C1_DOUT[2] = DFFEAS(C1_DOUT[2]_lut_out, CLK, VCC, , , , , , );

--C1L7 is REG7B:u2|DOUT[2]~58
--operation mode is arithmetic

C1L7 = CARRY(E1_q & (C1_DOUT[2] # !C1L5) # !E1_q & C1_DOUT[2] & !C1L5);


--C1_DOUT[3] is REG7B:u2|DOUT[3]
--operation mode is arithmetic

C1_DOUT[3]_carry_eqn = C1L7;
C1_DOUT[3]_lut_out = C1_DOUT[3] $ (C1_DOUT[3]_carry_eqn);
C1_DOUT[3] = DFFEAS(C1_DOUT[3]_lut_out, CLK, VCC, , , , , , );

--C1L9 is REG7B:u2|DOUT[3]~62
--operation mode is arithmetic

C1L9 = CARRY(!C1L7 # !C1_DOUT[3]);


--C1_DOUT[4] is REG7B:u2|DOUT[4]
--operation mode is arithmetic

C1_DOUT[4]_carry_eqn = C1L9;
C1_DOUT[4]_lut_out = C1_DOUT[4] $ (!C1_DOUT[4]_carry_eqn);
C1_DOUT[4] = DFFEAS(C1_DOUT[4]_lut_out, CLK, VCC, , , , , , );

--C1L11 is REG7B:u2|DOUT[4]~66
--operation mode is arithmetic

C1L11 = CARRY(C1_DOUT[4] & (!C1L9));


--C1_DOUT[5] is REG7B:u2|DOUT[5]
--operation mode is arithmetic

C1_DOUT[5]_carry_eqn = C1L11;
C1_DOUT[5]_lut_out = C1_DOUT[5] $ (C1_DOUT[5]_carry_eqn);
C1_DOUT[5] = DFFEAS(C1_DOUT[5]_lut_out, CLK, VCC, , , , , , );

--C1L31 is REG7B:u2|DOUT[5]~70
--operation mode is arithmetic

C1L31 = CARRY(!C1L11 # !C1_DOUT[5]);


--C1_DOUT[6] is REG7B:u2|DOUT[6]
--operation mode is normal

C1_DOUT[6]_carry_eqn = C1L31;
C1_DOUT[6]_lut_out = C1_DOUT[6] $ (!C1_DOUT[6]_carry_eqn);
C1_DOUT[6] = DFFEAS(C1_DOUT[6]_lut_out, CLK, VCC, , , , , , );


--F1_reg[7] is fsk_decode:u7|reg[7]
--operation mode is normal

F1_reg[7]_lut_out = H1_q_a[7];
F1_reg[7] = DFFEAS(F1_reg[7]_lut_out, CLK, VCC, , , , , , );


--F1_reg[2] is fsk_decode:u7|reg[2]
--operation mode is normal

F1_reg[2]_lut_out = H1_q_a[2];
F1_reg[2] = DFFEAS(F1_reg[2]_lut_out, CLK, VCC, , , , , , );


--F1_reg[1] is fsk_decode:u7|reg[1]
--operation mode is normal

F1_reg[1]_lut_out = H1_q_a[1];
F1_reg[1] = DFFEAS(F1_reg[1]_lut_out, CLK, VCC, , , , , , );


--F1_reg[0] is fsk_decode:u7|reg[0]
--operation mode is normal

F1_reg[0]_lut_out = H1_q_a[0];
F1_reg[0] = DFFEAS(F1_reg[0]_lut_out, CLK, VCC, , , , , , );


--F1L41 is fsk_decode:u7|process2~169
--operation mode is normal

F1L41 = F1_reg[2] # F1_reg[1] # F1_reg[0];


--F1_reg[4] is fsk_decode:u7|reg[4]
--operation mode is normal

F1_reg[4]_lut_out = H1_q_a[4];
F1_reg[4] = DFFEAS(F1_reg[4]_lut_out, CLK, VCC, , , , , , );


--F1_reg[5] is fsk_decode:u7|reg[5]
--operation mode is normal

F1_reg[5]_lut_out = H1_q_a[5];
F1_reg[5] = DFFEAS(F1_reg[5]_lut_out, CLK, VCC, , , , , , );


--F1_reg[3] is fsk_decode:u7|reg[3]
--operation mode is normal

F1_reg[3]_lut_out = H1_q_a[3];
F1_reg[3] = DFFEAS(F1_reg[3]_lut_out, CLK, VCC, , , , , , );


--F1_reg[6] is fsk_decode:u7|reg[6]
--operation mode is normal

F1_reg[6]_lut_out = H1_q_a[6];
F1_reg[6] = DFFEAS(F1_reg[6]_lut_out, CLK, VCC, , , , , , );


--F1L51 is fsk_decode:u7|process2~170
--operation mode is normal

F1L51 = F1_reg[4] & F1_reg[5] & F1_reg[3] & F1_reg[6] # !F1_reg[4] & (F1_reg[5] # F1_reg[3] # F1_reg[6]);


--F1L61 is fsk_decode:u7|process2~171
--operation mode is normal

F1L61 = F1_reg[7] & (F1_reg[4] # F1L51) # !F1_reg[7] & (!F1L51 # !F1_reg[4] # !F1L41);


--F1L2 is fsk_decode:u7|LessThan~315
--operation mode is normal

F1L2 = F1_q[1] # F1_q[2] # F1_q[3] # F1_q[4];


--F1L3 is fsk_decode:u7|LessThan~316
--operation mode is normal

F1L3 = !F1_q[5] & !F1_q[6] & !F1_q[7] & !F1L2;


--E1_q is ps7:u6|q
--operation mode is normal

E1_q_lut_out = !E1_c3;
E1_q = DFFEAS(E1_q_lut_out, !F1_q[7], VCC, , , E1L5, ls, , );


--E1_c3 is ps7:u6|c3
--operation mode is normal

E1_c3_lut_out = !E1_c2;
E1_c3 = DFFEAS(E1_c3_lut_out, !F1_q[7], !ls, , , , , , );


--E1_c2 is ps7:u6|c2
--operation mode is normal

E1_c2_lut_out = E1_c1;
E1_c2 = DFFEAS(E1_c2_lut_out, !F1_q[7], !ls, , , , , , );


--E1_c1 is ps7:u6|c1
--operation mode is normal

E1_c1_lut_out = !E1_c0;
E1_c1 = DFFEAS(E1_c1_lut_out, !F1_q[7], !ls, , , , , , );


--E1_c0 is ps7:u6|c0
--operation mode is normal

E1_c0_lut_out = !E1_c0;
E1_c0 = DFFEAS(E1_c0_lut_out, !F1_q[7], !ls, , !E1_c3, , , , );


--CLK is CLK
--operation mode is input

CLK = INPUT();


--ls is ls
--operation mode is input

ls = INPUT();


--count1[0] is count1[0]
--operation mode is output

count1[0] = OUTPUT(F1_q[0]);


--count1[1] is count1[1]
--operation mode is output

count1[1] = OUTPUT(F1_q[1]);


--count1[2] is count1[2]
--operation mode is output

count1[2] = OUTPUT(F1_q[2]);


--count1[3] is count1[3]
--operation mode is output

count1[3] = OUTPUT(F1_q[3]);


--count1[4] is count1[4]
--operation mode is output

count1[4] = OUTPUT(F1_q[4]);


--count1[5] is count1[5]
--operation mode is output

count1[5] = OUTPUT(F1_q[5]);


--count1[6] is count1[6]
--operation mode is output

count1[6] = OUTPUT(F1_q[6]);


--count1[7] is count1[7]
--operation mode is output

count1[7] = OUTPUT(F1_q[7]);


--dds1[0] is dds1[0]
--operation mode is output

dds1[0] = OUTPUT(H1_q_a[0]);


--dds1[1] is dds1[1]
--operation mode is output

dds1[1] = OUTPUT(H1_q_a[1]);


--dds1[2] is dds1[2]
--operation mode is output

dds1[2] = OUTPUT(H1_q_a[2]);


--dds1[3] is dds1[3]
--operation mode is output

dds1[3] = OUTPUT(H1_q_a[3]);


--dds1[4] is dds1[4]
--operation mode is output

dds1[4] = OUTPUT(H1_q_a[4]);


--dds1[5] is dds1[5]
--operation mode is output

dds1[5] = OUTPUT(H1_q_a[5]);


--dds1[6] is dds1[6]
--operation mode is output

dds1[6] = OUTPUT(H1_q_a[6]);


--dds1[7] is dds1[7]
--operation mode is output

dds1[7] = OUTPUT(H1_q_a[7]);


--dc_out is dc_out
--operation mode is output

dc_out = OUTPUT(F1_s);


--E1L5 is ps7:u6|c3~3
--operation mode is normal

E1L5 = !E1_c3;